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goa unit circuit and its driving method, goa circuit

A unit circuit and potential technology, applied in the direction of digital memory information, instruments, static memory, etc., can solve the problems of large power consumption, large occupied area, wide display device frame width, etc., to achieve power consumption and occupied area reduction, size Reduced effect

Active Publication Date: 2019-01-18
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] During the actual application process of the above-mentioned GOA circuit 100, the inventors found that the above-mentioned GOA circuit 100 consumes a lot of power and occupies a large area, resulting in a wide frame width of the display device.

Method used

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  • goa unit circuit and its driving method, goa circuit
  • goa unit circuit and its driving method, goa circuit
  • goa unit circuit and its driving method, goa circuit

Examples

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Effect test

Embodiment 1

[0042] As described in the background technology, the GOA circuit in the prior art has the disadvantages of large power consumption and occupied area. The inventors of the present invention have found through research that one of the reasons for the above disadvantages is:

[0043] Since the capacitive load on the gate line is very large relative to the internal capacitance of the GOA unit circuit 10, in order to ensure the normal driving and charging of the gate line, the second switch M2 in the GOA unit circuit 10 needs to be large enough. The size of the second switch M2 is several times to tens of times the size of other switch tubes in the GOA unit circuit 10 . In the GOA unit circuit 10, the clock control signal CLK is the signal with the highest frequency among the GOA control signals (including input signal Input, reset signal Reset, low-level power supply signal VGL, etc.), so the power consumption of the GOA unit circuit 10 is A large part is caused by the capacitive...

Embodiment 2

[0061] This embodiment provides a driving method for a GOA unit circuit, see Figure 4 and Figure 8 , the driving method is used to drive the GOA unit circuit 10 described in Embodiment 1, the driving method includes: a frame time includes an input period t1, an output period t2, a discharge period t3 and a reset period t4 in sequence.

[0062] In the input period t1, the input signal Input is at a high level, the first input module 1 is turned on, the potential of the PU point is pulled high, the pull-up module 2 is turned on, the first clock control signal CLK is at a low level, and the output terminal outputs a low level flat. At the same time, the reset signal Reset is at low level, and the reset module 4 is turned off. The second clock control signal CLKB is high level, the noise control module 6 is turned on, under the control of the high potential of the PU point, the second input module 5 is turned on, and the low-level power supply signal VGL is input to the PD poi...

Embodiment 3

[0075] Based on Example 1, such as Figure 9 As shown, the present embodiment provides a GOA circuit 100, the GOA circuit 100 includes a plurality of GOA unit circuits 10 connected in cascade, and the GOA unit circuits 10 are the GOA unit circuits 10 as described in the first embodiment. The cascading mode of each GOA unit circuit 10 in the GOA circuit 100 is:

[0076] In the GOA unit circuits 10 at each level, the D terminal of the GOA unit circuit 10 at the upper level is connected to the PU point of a certain subsequent level of the GOA unit circuit.

[0077] The CLK terminals and CLKB terminals of the odd-numbered GOA unit circuits are connected to the first group of clock signal input lines (CLK1 and CLKB1). In each odd-numbered GOA unit circuit, the Output end of the upper-level GOA unit circuit is connected to the Input end of the lower-level GOA unit circuit, and the Reset end of the upper-level GOA unit circuit is connected to the Output end of the lower-level GOA un...

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Abstract

The invention provides a GOA unit circuit, a driving method thereof, and a GOA circuit, which relate to the field of display technology and are used to solve the problems of high power consumption and large occupied area of ​​existing GOA circuits. The GOA unit circuit includes: a pull-up node, a first input module, a pull-up module, a first pull-down module, a reset module, a pull-down node, a second input module, a noise control module, a first denoising module and a second A denoising module, wherein the first pull-down module is connected to the output signal terminal, the first clock control signal terminal and the discharge signal terminal, and the high level of the discharge signal provided by the discharge signal terminal is higher than the high level of the input signal provided by the input signal terminal. level, the first pull-down module is used to discharge the output signal terminal under the control of the first clock control signal and the discharge signal, and pull the potential of the output signal terminal down to a low level. The aforementioned GOA unit circuit is used to drive the gate lines of the display device.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a GOA (Gate Driver on Array, array substrate row driving) unit circuit, a driving method thereof, and a GOA circuit. Background technique [0002] In the existing display technology, in order to achieve low cost, most display devices adopt GOA technology. GOA technology means that the GOA circuit for driving the gate line is arranged on both sides of the effective display area of ​​the array substrate of the display device (that is, the frame area) technology. The GOA circuit is used to realize the shift register function, that is, to provide an output signal row by row to all gate lines within a frame, and the output signal is a pulse signal with a certain pulse width to drive each gate line. [0003] The GOA circuit includes a plurality of GOA unit circuits, and each GOA unit circuit is correspondingly connected to a gate line. Such as figure 1 As shown, it is a str...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/20
CPCG09G3/20G09G2310/0267G09G2310/0286G11C19/28G09G2310/08G09G2330/021G09G2310/061
Inventor 张元波陈帅
Owner BOE TECH GRP CO LTD
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