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Stacked Conductive Interconnect Inductors

A technology for conductive interconnection and inductors, which can be used in inductors, fixed inductors, printed inductors, etc., and can solve problems such as low loss

Active Publication Date: 2018-10-26
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The same challenges of maintaining small feature sizes also apply to passive glass (POG) technologies, where high performance components such as inductors and capacitors are built on highly insulating substrates, which can also have very low losses

Method used

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  • Stacked Conductive Interconnect Inductors
  • Stacked Conductive Interconnect Inductors
  • Stacked Conductive Interconnect Inductors

Examples

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Embodiment Construction

[0016] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description contains specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. As described herein, use of the term "and / or" is intended to mean an "inclusive or", and use of the term "or" is intended to mean an "exclusive or".

[0017] Passive glass devices involve high performance inductor and capacitor components with several advantages over other technologies such as surface mount technology or multilayer ceramic chi...

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PUM

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Abstract

An integrated circuit device includes a first substrate supporting a pair of conductive interconnects, such as pillars. The device also includes a second substrate on the pair of conductive interconnects. The pair of conductive interconnects is arranged to operate as a first 3D solenoidal inductor. The device further includes conductive traces coupling the pair of conductive interconnects to each other.

Description

technical field [0001] The present invention relates generally to integrated circuit (IC) fabrication. More specifically, one aspect of the invention relates to stacked conductive interconnect inductors. Background technique [0002] The process flow of semiconductor manufacturing of integrated circuits (ICs) may include front-end-of-line (FEOL), middle-of-line (MOL) and back-end-of-line (BEOL) processes. The front-end process may include wafer preparation, isolation, full formation, gate patterning, spacers, extension and source / drain implants, silicide formation, and dual stress liner formation. The intermediate process may include gate contact formation. The back-end process may include a series of wafer processing steps for interconnecting semiconductor devices produced during the front-end and mid-end processes. [0003] The successful manufacture and qualification of modern semiconductor chip products involves the interaction between the materials and the processes ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L49/02H10N97/00
CPCH01L23/49833H01L28/10H01L2224/16225H01L2924/0002H01L2924/15311H05K1/0306H05K1/113H05K1/144H05K2201/042H05K2201/1003H01F17/0006H01F2017/0086H05K1/181Y10T29/4902H05K1/141H01L2924/00
Inventor D·D·金马里奥·弗朗西斯科·韦莱兹左诚杰章汉·霍比·云金郑海马修·迈克尔·诺瓦克
Owner QUALCOMM INC