Clock synchronization method

Abstract

The first synchronous FF is disposed at the starting point of the clock tree of the frequency-divided clock of each lower hierarchical block, and the first maximum delay time of the reference clock from the branch point of the reference clock and the frequency-divided clock to the first synchronous FF is acquired. The second maximum delay time of the reference clock between adjacent two of second synchronous FFs is determined so as to be less than half the period of the reference clock. The number of stages of the second synchronous FFs is determined according to the first and second maximum delay times. The target delay time from the branch point is determined so as to be not more than the second maximum delay time, and the second synchronous FF and a latch are disposed so as to achieve the target delay time.

Description

technical field [0001] The present invention relates to a clock synchronization method for synchronizing phases of a reference clock and a frequency-divided clock supplied from a clock generating circuit included in a top block to terminal FFs (flip-flops) included in a plurality of lower layer blocks. Background technique [0002] In the layout design of a large-scale semiconductor integrated circuit, a hierarchical layout design method is used. In the hierarchical layout design method, most circuits of a semiconductor integrated circuit are divided into a plurality of lower layer modules, and the layout design of each lower layer module is performed. Afterwards or at the same time, the layout design of the top modules other than the lower layer modules is performed, a clock signal is connected to each lower layer module, and wiring is connected between each lower layer module. [0003] In layout design of lower layer modules and top layer modules, a method called clock tr...

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Problems solved by technology

Since the clock path also changes in delay, it is difficult to design timing that satisfies the setup / hold constraints while considering the delay variation of the two paths.

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