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Digital background calibration device for pipeline adc

A calibration device and pipeline technology, applied in the field of ADC calibration, can solve the problems of complex circuit design, not considering the influence of calibration algorithm, etc., and achieve the effect of low calibration cost and high calibration accuracy

Inactive Publication Date: 2019-05-14
BEIJING JIAOTONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] The current calibration technology for pipeline ADCs generally changes the structure of the analog circuit, complicating the original circuit design, and does not consider the impact of the calibration algorithm itself on the pipeline ADC

Method used

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  • Digital background calibration device for pipeline adc
  • Digital background calibration device for pipeline adc
  • Digital background calibration device for pipeline adc

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0053] The embodiment of the present invention provides a digital background calibration device for pipeline ADC, the structural block diagram of the device is as follows figure 1 As shown, it consists of multi-stage cascaded sub-pipelines and calibration circuits, each sub-pipeline includes a sample / hold circuit, a margin amplifier, Sub-ADC and Sub-DAC, and the calibration circuit is connected to each sub-pipeline circuit .

[0054] The analog signal passes through each sub-pipeline of the pipeline ADC in turn. While the analog input is calibrated to the sub-pipeline, the PN sequence (Pseudo-noise Sequence, pseudo-random sequence) generated by the calibration circuit is input to the calibrated sub-pipeline. In the Sub-DAC of the pipeline, the analog output of the calibrated sub-pipeline and the pseudo-random sequence pass through the margin amplifier and then enter the subsequent sub-pipeline;

[0055] The calibration circuit uses the pseudo-random sequence and the calibrat...

Embodiment 2

[0076] The structural diagram of a digital background calibration device of a pipelined ADC composed of 7-stage sub-pipeline cascades provided by this embodiment is as follows image 3 As shown, each of the first 6 stages generates 1.5bit digital bits, and the seventh stage generates 2bit digital bits. The analog signal passes through each stage of the pipeline ADC in turn, and generates a 1.5bit (the last stage is 2bit) digital quantity, and finally obtains the final 8bit digital quantity through dislocation and addition.

[0077] Calibration only calibrates the first 4 levels, and the object of calibration is the error caused by the capacitance loss and the limited gain of the operational amplifier. When a certain stage structure needs to be calibrated, the pseudo-random sequence generated by the PN sequence generator will be input into the Sub-DAC of the calibrated stage while the analog quantity is input into the stage structure. The input analog quantity and the pseudo-r...

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Abstract

The invention provides a digital background calibration device for a pipeline ADC. The device comprises multiple cascaded sub pipelines and a calibration circuit. Each sub pipeline comprises a sampling / holding circuit, a residue amplifier, a Sub-ADC and a Sub-DAC. Analog signals pass through each sub pipeline of the pipeline ADC in order. A pseudo random sequence generated by the calibration circuit is input to the Sub-DAC of the calibrated-level sub pipeline while analog quantity is input to the calibrated-level sub pipeline. The calibration circuit uses the pseudo random sequence and digital values that are converted by all sub pipelines subsequent to the calibrated-level sub pipeline and are already calibrated to calibrate digital values that are converted by the calibrated-level sub pipeline, so as to obtain digital values which are converted by the calibrated-level sub pipeline and are already calibrated. The digital background calibration device of the invention overcomes the defects caused by modification of analog circuits as to existing calibration algorithms and can simultaneously correct errors caused by capacitor mismatch and finite gains of operational amplifiers, without interrupting normal work of ADCs or changing the original analog circuit design. In particular, errors introduced by the calibration algorithm are reduced, the calibration cost is low and the calibration accuracy is high.

Description

technical field [0001] The invention relates to the technical field of ADC (Analog-to-Digital Converter, analog-to-digital converter) calibration, in particular to a digital background calibration device for a pipeline ADC. Background technique [0002] ADC is a circuit module that converts analog signals into digital signals. It is widely used in various fields, such as audio and video acquisition, high-definition image processing, communication systems, etc. Different fields have different requirements for the performance of ADCs, and thus ADCs with different structures have been developed. Among them, the pipeline ADC takes into account the important characteristics of the two major ADC applications, speed and precision, so it is widely used. [0003] Today, with the advancement of manufacturing technology and the further reduction of transistor feature size, the design of high-speed and high-precision ADCs faces difficulties such as device scaling down and power supply ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10H03M1/38
CPCH03M1/1023H03M1/38
Inventor 骆丽王天伟
Owner BEIJING JIAOTONG UNIV