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DES algorithm round iteration system and method based on coarse-grained reconfigurable architecture

A coarse-grained, iterative technology, applied in the field of embedded reconfigurable systems, can solve problems such as method and system inapplicability

Active Publication Date: 2016-09-28
SOUTHEAST UNIV WUXI INST OF TECH INTEGRATED CIRCUITS
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Problems solved by technology

[0006] The existing Chinese patent 201510886219.0, the title of the invention is: a SHA256 implementation method and system based on a large-scale coarse-grained reconfigurable processor, which aims at the SHA256 method by partially expanding and The intermediate result data caching method is optimized and accelerated, but for the DES algorithm, this method and system are not applicable

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  • DES algorithm round iteration system and method based on coarse-grained reconfigurable architecture
  • DES algorithm round iteration system and method based on coarse-grained reconfigurable architecture
  • DES algorithm round iteration system and method based on coarse-grained reconfigurable architecture

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[0067] Below in conjunction with accompanying drawing and specific embodiment, further illustrate the present invention, should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention All modifications of the valence form fall within the scope defined by the appended claims of the present application.

[0068] A DES algorithm round iteration system based on a coarse-grained reconfigurable architecture, such as figure 1 shown, including the system bus, reconfigurable processor, and microprocessor. The microprocessor sends plaintext data to the reconfigurable processor through the system bus, and the plaintext data will be stored in the input FIFO register group, and after the final calculation is completed, the ciphertext data will be output to the output FIFO regist...

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Abstract

The invention discloses a DES algorithm round iteration system and method based on a coarse-grained reconfigurable architecture. The system comprises a system bus, a reconfigurable processor and a microprocessor. The reconfigurable processor comprises a configuration unit, an input first-in first-out register bank, an output first-in first-out register bank, a general register file, M reconfigurable array blocks and a lookup table. The advantages of parallel processing of the reconfigurable technology and independent configurability of a calculation module are utilized, and efficient calculation of a DES algorithm is performed through methods for improving the parallelism of the DES algorithm and optimizing an assembly line while the certain flexibility is supported.

Description

technical field [0001] The invention relates to a large-scale coarse-grained embedded reconfigurable system and a processing method thereof, which are applied in the fields of communication, encryption, etc., and belong to the field of embedded reconfigurable systems. Background technique [0002] General-purpose processors and application-specific integrated circuits (ASICs) are two mainstream methods in the field of traditional computer system architecture. However, with the increasing demand for system performance, energy consumption, time-to-market and other indicators in the application field, the disadvantages of these two traditional computing models are exposed. [0003] The general-purpose processor method has a wide range of applications, but the calculation efficiency is low. Although the application-specific integrated circuit can improve the calculation speed and calculation efficiency and meet the performance requirements, the flexibility of the ASIC device is ...

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Application Information

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IPC IPC(8): G06F9/315
CPCG06F9/30134
Inventor 杨锦江明畅尹玲申艾麟李兆奇赵利锋葛伟
Owner SOUTHEAST UNIV WUXI INST OF TECH INTEGRATED CIRCUITS
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