Double-mask self-aligning patterning method

Abstract

The invention discloses a double-mask self-aligning patterning method. The method comprises the following steps: taking a patterning photoresist as a first core, covering a first RELACS material layer on the surface of the first core, performing a first thermal-crosslinking reaction, and generating a first thermal-crosslinking reactant layer; removing a part of the first thermal-crosslinking reactant layer and the patterning photoresist, taking the residual first thermal-crosslinking reactant layer as a second core, covering a second RELACS material layer on the residual first thermal-crosslinking reactant layer, performing a second first thermal-crosslinking reaction, generating a second thermal-crosslinking reactant layer; finally removing a part of the second thermal-crosslinking reactant layer and the residual first thermal-crosslinking reactant layer in order, taking the second thermal-crosslinking reactant layer as the mask pattern, and forming the fine patterns having high density lines.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a double-mask self-alignment patterning method. Background technique [0002] In the process of manufacturing semiconductor devices, especially when the feature size of semiconductor devices is getting smaller and smaller, for fine patterns formed by alternately arranged lines (lines) and spaces (spaces) on the substrate, a double pattern ( Double-Patterning) technology, such as lithography-freeze-lithography-etch process (LFLE, Litho-Freeze-Litho-Etch), lithography-etch-lithography-etch (LELE, Litho-Etch-Litho- Etch) process and Self-Aligned Double Patterning (SADP, Self-Aligned Double Patterning) process, etc. [0003] Due to economic and process considerations, the existing technology tends to use the SADP process to form fine patterns, and the typical SADP process flow is as follows: Figure 1a to Figure 1d As shown, it includes: first, a sacrificial layer 102 is f...

AI Technical Summary

Problems solved by technology

[0006] With the development of semiconductor technology, the characteristic line width of semiconductor devices is gradually reduced. In the manufacturing process, it is expected to form fine patterns with higher density lines. Since the photoresist is limited by the exposure accuracy in the patterning process, it is used as the core The size of the photoresist cannot be reduced indefinitely, so the existing method is not suitable for the situation where high-density fine patterns are required

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