Address translation method and device

Abstract

The invention provides an address translation method and apparatus. The address translation method is characterized in that an address field label is added in a processor; and the corresponding relationship between address field values and page table items of a TLB (Translation Lookaside Buffer) is stored in the TLB of the processor. The address translation method comprises the steps: modifying the address field label as a first address field value corresponding to a virtual address to be translated through a preset program or a instruction prefix; in the corresponding relationship of the TLB of the processor, looking for a page table item corresponding to the first address field value; and according to the found page table item corresponding to the first address field value, translating the virtual address to be translated into a physical address. The address translation method solves the problem that as a special register for a virtual state mode is not suitable binary translation and a virtual standard is based on an MIPS (Microprocessor without interlocked piped stages) framework in the prior art, practicality and flexibility for address translation are lower if the virtual standard is used to perform address translation.

Description

technical field [0001] The invention relates to computer technology, in particular to an address translation method and device. Background technique [0002] In the current high-performance processors, since the address used by the program is a virtual address and the address used by the processor is a physical address, the processor is usually executed through a translation lookaside buffer (Translation Lookaside Buffer, referred to as: TLB). The speed of translation from the virtual address to the physical address (hereinafter referred to as: virtual-real address) is accelerated, specifically, the virtual-real address translation is performed through the page table stored in the TLB. In a Microprocessor without interlocked piped stages (MIPS for short) architecture, some virtual addresses can only be translated by pre-set rules in the processor without being processed by the TLB. [0003] In order to solve the problem that the translation of some virtual addresses in the ...

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Problems solved by technology

[0005] The present invention provides an address translation method and device to solve the virtualization specification based on the MIPS framework in the prior art. Since the special registers set for the virtual state mode are not suitable for binary translation, the virtualization specification is used to execute the address The problem of poor practicality and flexibility of translation

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