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Metal lead frame structure with low test cost and manufacturing method thereof

A technology of testing cost and metal leads, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problems of inability to test each connection relationship, no way to test products individually, low efficiency, etc. , to achieve the effect of reducing test cost, low test cost, improving quality management and efficiency

Active Publication Date: 2018-11-23
江阴芯智联电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The test is based on pieces, which is inefficient and time-consuming
[0003] The usual metal lead frame and MIS metal plated plastic packaging substrate, the pins of a single chip are connected, and the connection relationship of each individual chip cannot be tested on the substrate
With such a substrate as a carrier, there is no way to test each product individually after plastic sealing. It must wait until it is cut into independent units, and then these independent units are transported to the test unit with another carrier board (tray, bowl, reel). On the stage, such a test plan cannot be compared with the batch test plan in production

Method used

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  • Metal lead frame structure with low test cost and manufacturing method thereof
  • Metal lead frame structure with low test cost and manufacturing method thereof
  • Metal lead frame structure with low test cost and manufacturing method thereof

Examples

Experimental program
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Embodiment Construction

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0036] Such as figure 1 As shown, a low-test-cost metal lead frame structure in this embodiment includes a plurality of units, each unit includes pins, and the pins include a first metal layer 1 and a second metal layer 2, The second metal layer 2 is arranged on the front side of the first metal layer 1, and the mold compound 4 is filled between the pins, and the back side of the first metal layer 1 and the front side of the second metal layer 2 are provided with a third The metal layer 3 is provided with a groove 5 between the pins between two adjacent units, and the groove 5 isolates the pins between the two adjacent units.

[0037] Its manufacturing method is as follows:

[0038] Step 1, see figure 2 , take a metal substrate;

[0039] Step two, see image 3 , paste a photoresist film that can be exposed and developed on the front of t...

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PUM

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Abstract

The invention relates to a metal lead frame structure with a low test cost and a manufacturing method thereof, which belong to the technical field of semiconductor packaging. The metal lead frame structure comprises multiple units; each unit comprises a pin; the pin comprises a first metal layer (1) and a second metal layer (2); the second metal layer (2) is arranged on the front face of the first metal layer (1); gaps between the pins are filled with molding compounds (4); third metal layers (3) are arranged on the back face of the first metal layer (1) and the front face of the second metal layer (2); a groove (5) is arranged between pins of adjacent two units; and the groove (5) separates the pins of the adjacent two units. According to the metal lead frame structure with a low test cost and the manufacturing method thereof provided by the invention, a whole-process testable ability can be brought, the test cost can be greatly reduced, and the quality and the efficiency are improved.

Description

technical field [0001] The invention relates to a metal lead frame structure with low test cost and a manufacturing method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] The current packaging and testing are integrated, the substrate material needs to be tested, and various tests are required after packaging. The test is based on a piece, which is inefficient and time-consuming. [0003] The usual metal lead frame and MIS metal plated plastic packaging substrate, the pins of a single chip are connected, and the connection relationship of each individual chip cannot be tested on the substrate. With such a substrate as a carrier, there is no way to test each product individually after plastic sealing. It must wait until it is cut into independent units, and then these independent units are transported to the test unit with another carrier board (tray, bowl, reel). On the stage, such a test plan cannot be compared with the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L21/48
Inventor 张立东陈灵芝
Owner 江阴芯智联电子科技有限公司
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