Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Wafer-level packaging method for CMOS image sensor

An image sensor, wafer-level packaging technology, applied in the field of image sensors, can solve the problems of high thickness, high pixel product performance affecting image performance, etc., to achieve the effect of improving performance and reducing overall thickness

Active Publication Date: 2016-10-12
GALAXYCORE SHANGHAI
View PDF8 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This traditional CMOS image sensor has a high thickness after wafer-level packaging (including the thickness of the package body and the increased thickness of the surface assembly are too high), and affects the performance of the image, especially the performance of high-pixel products.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Wafer-level packaging method for CMOS image sensor
  • Wafer-level packaging method for CMOS image sensor
  • Wafer-level packaging method for CMOS image sensor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0024] Figure 1-Figure 10 It is a schematic diagram of the process of a wafer-level packaging method for a CMOS image sensor according to Embodiment 1 of the present invention.

[0025] like figure 1 As shown, a first wafer 100 is provided, and the first wafer 100 has a plurality of image sensor chips, shown here as two adjacent image sensor chips, and the image sensor chips have dicing lines between each other (indicated by dot-dash line), the image sensor chip has a photosensitive area 101 and a non-photosensitive area, the photosensitive area has pixel units, and the non-photosensitive area has pads 102 .

[0026] like figure 2 As shown, a second wafer 200 is provided, and several first grooves 201 are formed on the first surface 200A of the second wafer 200, and the first grooves 201 correspond to the photosensitive region 101 of the image sensor; Several second grooves 202 are formed on the first surface 200A, and the second grooves 202 correspond to the bonding pads...

Embodiment 2

[0036] Figure 11-Figure 20 It is a schematic diagram of the process of the wafer-level packaging method of the CMOS image sensor according to the second embodiment of the present invention.

[0037] like Figure 11As shown, a first wafer 1100 is provided, the first wafer 1100 has a plurality of image sensor chips, here shown as two adjacent image sensor chips, the image sensor chips have dicing lines between each other (indicated by dot-dash line), the image sensor chip has a photosensitive area 1101 and a non-photosensitive area, the photosensitive area has pixel units, and the non-photosensitive area has pads 1102 .

[0038] like Figure 12 As shown, a second wafer 1200 is provided, and several first grooves 1201 are formed on the first surface 1200A of the second wafer 1200, and the first grooves 1201 correspond to the photosensitive regions 1101 of the image sensor; Several second grooves 1202 are formed on the first surface 1200A, and the second grooves 1202 correspon...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Depthaaaaaaaaaa
Widthaaaaaaaaaa
Depthaaaaaaaaaa
Login to View More

Abstract

Provided in the invention is a wafer-level packaging method for a CMOS image sensor. According to the method, a contact can be formed in a light-sensing surface of a chip by various ways of a ball grid array (BGA), a bump, and a lead; and assembling is carried out by silver paste connection, anisotropic conductive film (ACF) connection, pulse welding connection, ultrasonic connection, and solder ball thermal connection and the like. Therefore, the overall thickness after packaging is reduced effectively; and the image sensor performance is improved. The method is especially suitable for a high-pixel CMOS image sensor product and is also suitable for wafer-level packaging of a multi-camera module group product.

Description

technical field [0001] The invention relates to the field of image sensors, in particular to a wafer-level packaging method for a CMOS image sensor. Background technique [0002] Traditional wafer-level packaging of CMOS image sensors usually uses wafer-level glass to bond wafer-level chips through a certain height of the bank (DAM), grinds the back of the wafer to make leads and ball grid arrays (BGA), and cuts into A package structure that encapsulates a single chip. This traditional CMOS image sensor has a high thickness after wafer-level packaging (including the thickness of the package body and the increased thickness of the surface assembly are too high), and affects the performance of the image, especially the performance of high-pixel products. Contents of the invention [0003] The purpose of the present invention is to provide a wafer-level packaging method for a CMOS image sensor, which reduces the overall thickness of the package and improves the performance o...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L27/146
CPCH01L27/14687H01L27/1469
Inventor 赵立新邓辉
Owner GALAXYCORE SHANGHAI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com