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FPGA-based BISS-C protocol universal controller

A controller and storage controller technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problem of limited number of slave devices

Active Publication Date: 2016-11-02
严格集团股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention solves the problem that the number of slave devices supported by the existing BISS-C controller is limited

Method used

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  • FPGA-based BISS-C protocol universal controller
  • FPGA-based BISS-C protocol universal controller
  • FPGA-based BISS-C protocol universal controller

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Embodiment Construction

[0034] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, wherein the schematic embodiments and descriptions are only used to explain the present invention, but not as improper limitations to the present invention.

[0035] The overall design of the controller of the invention is compact in structure, powerful in function and flexible in application. It can be easily integrated into mainstream FPGA devices such as xlinx, Altera, and Lattice, and can be directly integrated into verilog circuits, or further packaged into peripheral IP cores of processors. The BISS-C protocol controller of the present invention realized with Lattice FPGA (model is: LCMXO2-1200HC-4TG100C), wherein, the occupancy rate of the register resource of FPGA is 28%, the utilization rate of SLICE resource is 58%, and the utilization rate of LUT4 resource The utilization rate is 57%, meeting the design requirements.

[0036] see f...

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PUM

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Abstract

The invention discloses an FPGA-based BISS-C protocol interface controller which comprises a frame transceiver, a register file, a memory controller, a first-in-first-out single-period actuator data queue SCDA_FIFO memory, and a first-in-first-out single-period sensor data queue SCDS_FIFO memory, wherein the memory controller comprises an external channel information read only memory NDT_ROM interface, which is connected with an external channel information read only memory NDT_ROM. The NDT_ROM stores multi-channel description information of a plurality of devices.

Description

【Technical field】 [0001] The invention relates to the field of controllers supporting BISS-C protocol. 【Background technique】 [0002] For a long time, encoder manufacturers have relied on analog signals or simple digital incremental signal interfaces to communicate position information. Over time and encoder technology has evolved, with new processing methods and high levels of integration, allowing encoders to generate high-resolution position data, and adding advanced features such as commands, register communication, and more. It is therefore necessary to implement a new interface with features suitable for this high-end device. SSI is an outdated industry standard that cannot meet the speed and functionality requirements of manufacturers. A small number of manufacturers have launched their own protocols, but they are very closed, and there are incompatibilities between different brands of products. In 2002, iC-Haus launched the BiSS open interface. The purpose of Bi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
CPCG06F13/385
Inventor 王飞赵亮白相林李增强张岩岭
Owner 严格集团股份有限公司
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