A multi-chip frame package structure and manufacturing method thereof

Abstract

An embodiment of the present invention provides a multi-chip frame package structure, the package structure includes: at least one chip stage, at least one bottom chip and at least one upper chip; the at least one chip stage is used to accommodate the at least A bottom chip and the at least one upper chip; the packaging structure also includes: at least one first dielectric layer; wherein, the first dielectric layer is placed above the bottom chip; the upper chip is placed on the above the first dielectric layer; by adjusting the inclination angle of the first dielectric layer, the positional relationship between the bottom chip and the upper chip can be adjusted, so as to increase the number of chips stacked on the at least one carrier stage quantity. The embodiment of the present invention also provides a manufacturing method of the multi-chip frame packaging structure.

Description

technical field [0001] The invention relates to semiconductor device packaging technology, in particular to a multi-chip frame packaging structure and a manufacturing method thereof. Background technique [0002] Today, with the gradual development of electronic engineering, miniaturized, lightweight and functional integrated circuit (IC) chips are becoming more and more popular. Moreover, as the semiconductor industry's crystal garden process is about to reach the bottleneck, packaging technology will become an important role in improving chip manufacturing profits and challenging Moore's Law. Under this huge demand, semiconductor packaging density will continue to increase. From the development of one component, it has gradually entered the stage of integrating multiple components into a system. As a multi-chip packaging technology, system-in-package (SiP) is the current and future development trend of packaging technology. Its packaging forms are diverse, and according ...

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Problems solved by technology

[0003] QFP (Quad Flat Package) is a surface-mount package. The connection between the internal chip and the board level is completed by leading out pins of different shapes on the four sides. Because the size of the carrier table used to place the chip in the QFP middle frame is related to the size of the chip The number of pins is closely related, so it limits the feasibility of implementing SiP with QFP

Currently, frame-type packaging is usually used to realize SiP. However, when completing SiP packaging, the size of different components will seriously restrict the packaging density. Especially for thinner products, the number of packageable components becomes the frame-type packaging to carry forward SiP technology more serious problems

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