Thin-film transistor array substrate, display panel and display device

Abstract

The invention discloses a thin-film transistor array substrate, a display panel and a display device. The thin-film transistor array substrate mainly comprises the components of a substrate; a plurality of gate wires and data wires which are arranged on the substrate and are crossed with and insulated from one another; and a plurality of pixel units which are arranged in an area that is defined by the gate wires and the data wires, wherein each pixel unit comprises a switch element; an insulating layer which is arranged on the switch element and is provided with a through hole; and a pixel electrode which is arranged on the insulating layer and is electrically connected with the switch element through the through hole, wherein two pixel units which are adjacent in the extending direction of the gate wires share one through hole, so that a large-enough distance between the two through holes which are adjacent in the transverse direction is realized, thereby well placing insulating columns, thereby preventing problems of low standing stability and easy slippage of the insulating columns, and furthermore ensuring high thickness uniformity and relatively high surface pressure resistance.

Description

[0001] The application of the present invention is a divisional application of the invention application with the filing date of June 5, 2014, the application number of 201410246489.0, and the title of the invention "A Thin Film Transistor Array Substrate, Display Panel and Display Device". technical field [0002] The invention relates to the field of display technology, in particular to a thin film transistor array substrate, a display panel and a display device. Background technique [0003] In the existing liquid crystal display (Liquid Crystal Display, LCD) pixel structure, especially for the pixel structure in In-Plane Switching (In-Plane Switching, IPS) and Fringe Field Switching (Fringe Field Switching, FFS) mode, in order to make The electric field is uniform in the horizontal direction, and a planarization layer (Planarization, PLN) will be formed before forming the pixel electrodes. And form uniformly distributed through holes 101 in the PLN layer (such as figure...

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Problems solved by technology

[0004] When the size of each sub-pixel is reduced in order to increase the pixel display density of the LCD, the PLN holes need to maintain the original size due to process limitations, so that the distance between adjacent PLN holes is relatively close, which will lead to isolation of the photoresist material If there is an arc at the support position where the column is located, the photoresist material isolation column cannot be in full contact with the lower substrate. When the vacuum bonding is poor, the photoresist material isolation column is easy to slide into the PLN hole, resulting in The thickness of the cell at the location of the material isolation column is relatively low; moreover, during manual operation, the sliding of the photoresist material isolation column can easily lead to scratches on the alignment film

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