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How to optimize sonos memory settings to improve product yield

A technology of setting value and product, applied in the manufacturing process of SONOS memory, optimizing the setting value of SONOS memory to improve the field of product yield, to achieve the effect of improving product yield, reducing product failure rate, and optimizing distribution

Active Publication Date: 2019-01-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] figure 1 is the yield distribution map of a SONOS memory product, from figure 1 It can be seen that the proportion of product yield rate lower than 80% due to VT failure (that is, VT does not meet product specifications) is as high as 17.8%
It can be seen that VT failure is an important reason for the reduction of the yield rate of SONOS memory products. How to reduce the VT failure rate so as to improve the product yield rate is an urgent problem in this field.

Method used

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  • How to optimize sonos memory settings to improve product yield
  • How to optimize sonos memory settings to improve product yield
  • How to optimize sonos memory settings to improve product yield

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Embodiment Construction

[0027] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0028] figure 2 It is the VTP (turn-on voltage of the memory after programming) / VTE (turn-on voltage of the memory after erasure) distribution corresponding to different wafers (chips) of the same product, and the VT window of the memory unit device is defined as: the worst VTP value minus Worst VTE value. Such as figure 2 As shown, the VT of wafer1 and wafer2>=SPEC (the voltage value range required by the specification); the VT of waferM and waferN<SPEC, it can be seen that the VT of waferM and wafer N does not meet the specification, that is, the VT is invalid.

[0029] image 3 for figure 2 After applying the present invention to the product, after optimizing the setting value of the failed chip through local adjustment, the schematic diagram of the distribution of VTP (the turn-on voltage of the memory after programming) / VTE (the tu...

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Abstract

The invention discloses a method for optimizing the set value of SONOS memory to improve product yield. The method reduces the VT failure rate by optimizing and adjusting part of the set value of the failed chips whose VT does not meet the specification after chip screening, thereby improving Product yield. The method can effectively reduce the VT failure rate, significantly improve the product yield rate, and optimize the VT distribution under the premise of neither changing the specifications of the memory unit device nor affecting the reliability of the product.

Description

technical field [0001] The invention belongs to the field of manufacturing technology of semiconductor integrated circuits, and in particular relates to a manufacturing process method of a SONOS memory, in particular to a method for optimizing the setting value of the SONOS memory and improving the product yield. Background technique [0002] SONOS memory (Silicon-Oxide-Nitride-Oxide-Silicon, a memory using silicon nitride as a charge storage medium) has become one of the main types of flash memory because of its good scaling characteristics and radiation resistance characteristics. [0003] At present, the VT (threshold voltage) window drift of memory cell devices due to process differences or drift is common in SONOS memories. This difference can exist within a wafer, within a batch, or even within a platform. VT includes VTP and VTE. VTP refers to the turn-on voltage of the memory after programming, and VTE refers to the turn-on voltage of the memory after erasing. The me...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66H01L27/11568H10B43/30H10B69/00
CPCH01L22/20H10B43/30
Inventor 单园园宋旻皓陈瑜陈华伦姚翔
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP