Quick test technology of EEPROM (Electrically Erasable Programmable Read-Only Memory)

Abstract

The invention discloses a quick test technology of an EEPROM (Electrically Erasable Programmable Read-Only Memory). The quick test technology is characterized in comprising a test control module, a high-voltage control module, a data reading module, a data comparison module, a logic control module, a data judgment module and a memory cell in the EEPROM. The data writing and reading of the EEPROM is completely controlled by internal logic to be finished, in addition, a data comparison process and a test judgment process are controlled by the internal logic to be realized, and finally, only a test result signal needs to be sent out. Test efficiency is very high. In a test process, written data does not adopt checkerboard test data (0x55 and 0xAA) but adopts 0x00and 0xFF test data which can be easily erased and written by the EEPROM to finish a test, and therefore, the test efficiency can be greatly improved. The whole test process of the test method hardly depends on external test resources.

Description

technical field [0001] The invention relates to the field of testing, in particular to a fast testing technology for EEPROM memory. Background technique [0002] The current electronic erasable rewritable read-only memory circuit or IP test usually adopts a checkerboard test method, that is, for the EEPROM memory circuit or IP to be tested, first write 0x55 data to all bytes, and then write the EEPROM memory The data in is read out and compared. Then also write 0xAA data to all bytes of the EEPROM memory, and then read and compare the data of the EEPROM memory. [0003] Writing data to the EEPROM memory can only be completed by erasing and programming the entire page at the fastest, which requires a lot of writing test time. In addition, limited by the number of IO PADs in general products, the test data is generally transmitted in a serial manner, and the test time is also very long. The significant disadvantages of this method of testing are therefore: [0004] 1. Writ...

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Problems solved by technology

[0003] Writing data to the EEPROM memory can only be completed by erasing and programming the entire page at the fastest, which requires a lot of writing test time

In addition, due to the limitation of the number of IO PADs in general products, the test data is generally transmitted in a serial manner, and the test time is also very long.

The significant disadvantages of this testing method are therefore:

[0004] 1. Writing data to the EEPROM memory can only be written page by page, which takes too much time

[0005] 2. Most of the reading and writing data of EEPROM is transmitted in serial mode, which needs to go through a serial-to-parallel conversion circuit, which also consumes a lot of test time

[0006] 3. The entire test is highly dependent on the external machine, and it is necessary to synchronize the external test machine to compile the test code, which consumes more test resources

[0007] 4. Chip products that have passed the checkerboard test have internal memory data of 0xAA, which is generally not suitable for direct delivery and needs to be erased again

This will inevitably consume more testing time

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