PIP capacitor manufacturing method, PIP capacitor and EEPROM storage unit

Abstract

The invention discloses a PIP capacitor manufacturing method, a PIP capacitor and an EEPROM storage unit. The manufacturing method comprises: forming a first polysilicon layer on a semiconductor substrate; forming a second polysilicon layer on both side walls of the first polysilicon layer, and making the surface of the second polysilicon layer in arc-shaped connection with the upper surface of the first polysilicon layer; forming an insulating layer covering the first polysilicon layer and the second polysilicon layer; and forming a third polysilicon layer on the insulating layer. By forming the second polysilicon layer, whose surface is in arc-shaped connection with the upper surface of the first polysilicon layer, on both side walls of the first polysilicon layer, vertical corners of the first polysilicon layer become smooth, thereby reducing partial discharge of the insulating layer and breakdown of the PIP capacitor which may caused by the vertical corners and further increasing the withstand voltage of the PIP capacitor.

Description

technical field [0001] The present application relates to the technical field of semiconductor integrated circuits, in particular, to a manufacturing method of a PIP capacitor, a PIP capacitor and an EEPROM storage unit. Background technique [0002] The upper and lower electrodes of the PIP (polysilicon / insulating layer / polysilicon) capacitor are polysilicon, and the electrodes of the PIP capacitor can be formed together with the polysilicon gate in the MOS device, so that the production of the PIP capacitor can be compatible with the production of the MOS device, and then The manufacturing cost of the PIP capacitor is reduced. Based on the above reasons, PIP capacitors are widely used in the manufacture of semiconductor devices. [0003] Such as figure 1 As shown, the existing PIP capacitor includes a tunnel oxide layer 20 ′ and a first polysilicon layer 30 ′ sequentially disposed on a semiconductor substrate 10 ′, and an insulating layer 40 disposed on the surface of th...

AI Technical Summary

Problems solved by technology

The first polysilicon layer 30' of the PIP capacitor formed by this method has a vertical corner, which will cause the electric field between the first polysilicon layer 30' and the second polysilicon to be uneven, and easily The position near the vertical corner generates a relatively high electric field, which easily causes partial discharge of the insulating layer 40' located near the vertical corner, and then causes the PIP capacitor to be easily broken down, and makes the PIP capacitor have a smaller withstand voltage. Voltage

[0004] Due to the small withstand voltage of PIP capacitors, its application in high-voltage devices is limited

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