Digital pulse width modulator based on delayed phase modulation

Abstract

The invention discloses a digital pulse width modulator based on delayed phase modulation. The digital pulse width modulator is composed of a clock generating module, a synchronous counting module, a delayed phase modulation module and an asynchronous signal generating module. The clock generating module performs frequency multiplication on an input clock signal and outputs a fundamental clock signal to the synchronous counting module, simultaneously delays the fundamental clock signal and outputs the delayed clock signal to the delayed phase modulation module. The synchronous counting module finishes coarse adjustment of the pulse width and respectively outputs an initial control signal and a coarse-adjusted control signal to the asynchronous signal generating module and the delayed phase modulation module. The delayed phase modulation module delays the coarse-adjusted control signal for generating eight paths of termination control signals and selects one path of termination control signal for outputting to the asynchronous signal generating module. The initial control signal and the termination control signal are input into an RS trigger in the asynchronous signal generating module and a final DPWM signal is output. The digital pulse width modulator improves modulation precision on the condition of no fundamental clock signal change and furthermore has advantages of relatively high accuracy, high versatility and high applicability.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a digital pulse width modulation circuit. Background technique [0002] In the system structure using digital pulse width modulation (Digital Pulse Width Modulation, DPWM), the main methods currently used are hybrid DPWM (Hybrid DPWM), and the second is DPWM realized by Dither method. The DPWM implemented by the Dither method is mainly realized by the idea of ​​​​the design. This design can use a low-precision and high-frequency DPWM to achieve a high effective output accuracy, which also reduces the power consumption and area of ​​​​the DPWM. However, the DPWM realized by the Dither method will generate a cycle delay when the mode is switched, which is not good for the high-speed response of the DPWM. Hybrid DPWM designs have no unwanted delays. [0003] The hybrid DPWM combines the traditional counter structure and the delay chain structure, and is usually com...

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Problems solved by technology

However, this method has the following disadvantages: the basic clock signal frequency of this method is only 1MHz, and its structure is complex, the design process requirements are high, and the cost is relatively high

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