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A fabrication method and structure of an epitaxial wafer for a superjunction device

A technology for superjunction devices and epitaxial wafers, which is applied in the field of manufacturing methods and structures of epitaxial wafers, can solve problems such as complex manufacturing processes of epitaxial wafers, and achieve the effects of reducing complexity, saving production costs, and simplifying process steps.

Active Publication Date: 2020-03-06
FOUNDER MICROELECTRONICS INT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In order to solve the problem of complex manufacturing process of epitaxial wafers of super junction devices, the present invention provides a method and structure for manufacturing epitaxial wafers of super junction devices

Method used

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  • A fabrication method and structure of an epitaxial wafer for a superjunction device
  • A fabrication method and structure of an epitaxial wafer for a superjunction device
  • A fabrication method and structure of an epitaxial wafer for a superjunction device

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Embodiment 1

[0031] Such as figure 1 As shown, it is a flowchart of a method for manufacturing an epitaxial wafer for a super-junction device provided in Embodiment 1 of the present invention, and the method includes:

[0032] S101. Doping the second conductivity type dopant through the first surface of the first conductivity type semiconductor single wafer to form a second conductivity type doped region in the first conductivity type semiconductor single wafer;

[0033] S102, forming alternately adjacent multiple grooves and multiple mesas in the doped region of the second conductivity type, and the bottoms of the multiple grooves are in contact with the single wafer of the first conductivity type;

[0034] S103, growing epitaxy of the first conductivity type, filling the trench and covering the upper surface of the mesa to form an epitaxial layer of the first conductivity type;

[0035] S104. Using the epitaxial layer of the first conductivity type as a substrate of a super junction dev...

Embodiment 2

[0048] The technical solution of the present invention will be described in detail below by taking an N-type semiconductor as an example. As used herein, references to conductivity types are limited to the described embodiments. However, those skilled in the art know that the P-type conductivity can be swapped for the N-type conductivity and the device will still function correctly. Such as Figure 3(a)~3(e) As shown in FIG. 2 , it is a schematic structural diagram of each stage in the manufacturing process of the epitaxial wafer for super-junction devices disclosed in Embodiment 2 of the present invention.

[0049] In the first step, as shown in FIG. 3( a ), an N-type silicon single wafer 1 is used to clean both the first surface 101 and the second surface 102 of the single wafer 1 .

[0050] In the second step, as shown in FIG. 3( b ), P-type thermal diffusion is performed on the single wafer 1 through the first surface 101 to form a P-type doped region 2 on the single waf...

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Abstract

The invention relates to a semiconductor manufacturing field, particularly to a manufacturing method and a structure of an epitaxial wafer for a super-junction device. The manufacturing method comprises the steps of performing doping of a second conductive type doping agent through the first surface of a first conductive type semiconductor single crystal wafer, and forming a second conductive type doped region in the first conductive type semiconductor single crystal wafer; forming multiple trenches and multiple table surfaces which are adjacent alternately in the second conductive type doped region, wherein the bottoms of the multiple trenches are in contact with the first conductive type semiconductor single crystal wafer; enabling first conductive type epitaxy to be grown, filling the trenches and covering the upper surfaces of the table surfaces to form a first conductive type epitaxial layer; and taking the first conductive type epitaxial layer as a substrate of the super-junction device. By adoption of the manufacturing method and the structure of the epitaxial wafer for the super-junction device, the problem of complex manufacturing process of the epitaxial wafer for the super-junction device is solved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method and structure of an epitaxial wafer used for a superjunction device. Background technique [0002] The drain and source poles of the trench type vertical double diffused field effect transistor (VDMOS) are on both sides of the device respectively, so that the current flows vertically inside the device, increasing the current density, improving the rated current, and the on-resistance per unit area is also small , is a very versatile power device. [0003] Traditional power metal-oxide-semiconductor field-effect transistors (MOSFETs) usually adopt a VDMOS structure. In order to withstand high withstand voltage, it is necessary to reduce the doping concentration of the drift region or increase the thickness of the drift region. The direct consequence of this is a sharp increase in the on-resistance. Super-junction MOSFETs use alternate P-N structur...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06
CPCH01L29/0634
Inventor 李理马万里赵圣哲
Owner FOUNDER MICROELECTRONICS INT