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A test method and chip

A test method and chip technology, which is applied in the electronic field, can solve the problems of limited number of chips and affect test efficiency, and achieve the effect of reducing the number of probes, reducing interfaces, and improving test efficiency

Active Publication Date: 2019-03-08
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] When the x8 data interface type ONFI uses the above test method for wafer testing, each chip needs 16 probes. Similarly, the x16 data interface type ONFI needs more probes, and the number of probes of the tester is Limited, so the number of chips tested by this test method is limited, which seriously affects the test efficiency

Method used

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Experimental program
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Embodiment 1

[0053] refer to figure 1 , which shows a flow chart of the steps of Embodiment 1 of a test method of the present invention, which may specifically include the following steps:

[0054] Step 101, inputting a voltage to the chip through a fixed voltage interface of the chip;

[0055] The embodiment of the present invention can be applied to wafer testing of chips. The wafer test is to test each die on the wafer to test some basic device parameters. A probe made of gold wire is installed on the detection head, and the contact PAD on the die Contact, test its electrical characteristics, the unqualified grains will be marked, and then when the wafer is cut into independent grains according to the grain, the marked unqualified grains will be eliminated, and no further processing will be carried out. A manufacturing process, so as not to increase the manufacturing cost.

[0056] In the embodiment of the present invention, the above-mentioned voltage is used to drive the chip to en...

Embodiment 2

[0070] refer to figure 2 , shows a flow chart of the steps of Embodiment 2 of a test method of the present invention, which may specifically include the following steps:

[0071] Step 201, inputting a voltage to the chip through a fixed voltage interface of the chip;

[0072] Step 202: Input a control command to the chip through the data and command interface of the chip, and stop inputting the voltage to the chip after the input of the control command is completed;

[0073] Step 203, after inputting the control instruction to the above-mentioned chip, input the identification instruction to the above-mentioned chip through the above-mentioned data and instruction interface;

[0074] Step 204, after inputting the identification instruction to the above-mentioned chip, input the data content in bit form to the above-mentioned chip through the above-mentioned data and instruction interface; wherein, the above-mentioned data content includes at least one of the following types:...

Embodiment 3

[0081] refer to image 3 , shows a flow chart of the steps of Embodiment 3 of a test method of the present invention, which may specifically include the following steps:

[0082] Step 301, inputting a voltage to the chip through a fixed voltage interface of the chip;

[0083] Step 302: Input a control command to the chip through the data and command interface of the chip, and stop inputting the voltage to the chip after the input of the control command is completed;

[0084] Step 303, after inputting the control instruction to the above-mentioned chip, input the identification instruction to the above-mentioned chip through the above-mentioned data and instruction interface;

[0085] Step 304, after inputting the identification instruction to the above-mentioned chip, input the data content in bit form to the above-mentioned chip through the above-mentioned data and instruction interface; wherein, the above-mentioned data content includes at least one of the following types: ...

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Abstract

An embodiment of the invention provides a test method and a chip, wherein the test method comprises the specific steps of inputting a voltage to the chip through a fixed voltage interface of the chip; inputting a control command to the chip through a data and command interface of the chip, and stopping inputting the voltage to the chip after the inputting of the control command; after inputting the control command to the chip, inputting an identifier command to the chip through the data and command interface; after inputting the identifier command to the chip, inputting data content of bit form to the chip through the data and command interface, wherein the data content includes at least one of command type, address type and data type; after inputting the data content of bit form to the chip, recognizing the type of the data content according to the identifier command; testing the chip according to the data content and the recognized type of the data content to obtain test results. The embodiment of the invention provides improved test efficiency.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a testing method and a chip. Background technique [0002] With the rapid growth of the portable electronic product market, the chips used in these electronic products have also developed rapidly, and testing is an important factor to determine whether the chip can be mass-produced. [0003] Existing Open NAND Flash Interface (Open NAND Flash Interface, ONFI) is divided into x8 and x16 two kinds of data interface types, wherein, the ONFI of x8 data interface type has 8 input / output (input / output, I / O) interfaces, NAND FLASH of x16 data interface type has 16 I / O interfaces. [0004] Taking ONFI of the x8 data interface type as an example, the existing test method data is input through the I / O interface in the form of bytes, and the test interfaces used include: chip select PAD_CEB, read clock input PAD_REB, write clock input Terminal PAD_WEB, address latch enable PAD_ALE, in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26
Inventor 苏志强丁冲陈立刚谢瑞杰
Owner GIGADEVICE SEMICON (BEIJING) INC
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