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A ddr2 DRAM ODT structure that reduces the influence of power supply network resistance

A technology of DDR2DRAMODT and power supply network, which is applied in the field of circuit structure of DDR2DRAM terminal resistance, can solve problems such as resistance deviation, and achieve the effect of simple structure

Active Publication Date: 2019-05-17
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The present invention proposes a DDR2 DRAM ODT structure that reduces the influence of power supply network resistance, aiming to overcome the problem of resistance deviation in different modes in the prior art

Method used

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  • A ddr2 DRAM ODT structure that reduces the influence of power supply network resistance
  • A ddr2 DRAM ODT structure that reduces the influence of power supply network resistance

Examples

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Embodiment Construction

[0022] This embodiment is a solution to the resistance deviation in the 150 ohm and 100 ohm modes. When ODT is turned on, VDDQ becomes vddq_local after passing through the power network resistor Rvddq, and a voltage difference is generated between VDDQ and vddq_local, and this voltage difference increases as Rvddq increases.

[0023] like figure 2 As shown, the voltage difference between VDDQ and vddq_local is converted into a voltage signal vout through the voltage comparison module. An NMOS transistor (N2) is connected in parallel on the side of the fixed resistance (R0) of the resistance module 2, and an NMOS transistor (N3) is connected in parallel on the side of the fixed resistance (R0) of the resistance module 3. The size of the NMOS transistor N3 is about twice the size (channel width) of the NMOS transistor N2. The gates of NMOS transistors N3 and N2 are connected to vout.

[0024] When set to 150 ohm mode, resistor module 1 and resistor module 2 are turned on, an...

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Abstract

The invention provides a DDR2 (double data rate 2) DRAM (dynamic random access memory) ODT (on die termination) structure for reducing resistance influence on a power network and solves the problem that the prior art experiences resistance deviations at different resistance modes. The DDR2 DRAM ODT structure is provided with a voltage comparison module and a signal conversion circuit, the voltage comparison module acquires component voltage of resistance Rvddq on the power network, the component voltage is converted by the signal conversion circuit into compensating resistance in independent parallel connection with fixed resistance R0 in a resistance module of other resistance value, and the value of the compensating resistance decreases with increase in the component voltage. The resistances in other resistance modes are subjected to feedback adjustment by using the component voltage of the resistance Rvddq on the power network, the resistances of the resistance modules corresponding to other modes decrease with the increase in the resistance Rvddq, and differences due to the resistance Rvddq in different resistance modes are eliminated.

Description

technical field [0001] The invention relates to a circuit structure of a DDR2 DRAM terminal resistor. Background technique [0002] In DDR2 DRAM, in order to improve signal integrity, each data interface module provides a termination resistor (ODT: On Die Termination), wherein the ODT resistor includes a pull-up resistor and a pull-down resistor. This patent application is mainly aimed at the situation of the pull-up resistor. The pull-up resistor can provide 3 modes of resistance value: 100 ohms or 150 ohms or 300 ohms. [0003] Traditional designs such as figure 1 As shown, there are three identical resistor modules (resistance module 1, resistor module 2, and resistor module 3), each of which includes a fixed resistor (R0) and an adjustable resistor (Rx). It also includes a resistance configuration module, for example, the resistance mode can be set to 300 ohms, 150 ohms or 100 ohms through the resistance configuration module. It also includes a resistance adjustment m...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/4094
CPCG11C11/4094
Inventor 刘海飞
Owner XI AN UNIIC SEMICON CO LTD