Multi-channel lvds clock line detection method and system

Abstract

The invention relates to a multipath LVDS clock line detection method and system. Multipath LVDS signals are received, and clock signals of one path of the LVDS signals are obtained as basic clock signals. Sampling clock signals are obtained by performing frequency multiplication processing according to the basic clock signals, and constant clock data is obtained by sampling the basic clock signals. Bit alignment processing is performed on the clock signals and data signals in each path of the LVDS signals according to the constant clock data and constant data, and the constant clock data corresponding to the basic clock signals are enabled to be consistent with the constant data. The constant clock data corresponding to the clock signals is obtained by collecting the clock signals after the bit alignment processing is performed on the clock signals in each path of the LVDS signals, and if the constant clock data corresponding to the clock signals are not consistent with the constant data, clock line fault prompt information is output. Detection is performed after the bit alignment processing is performed on each path of the clock signals, such that image abnormities of a display screen, caused by faults existing in an undetected clock line are avoided, and the reliability of multipath LVDS clock line detection is improved.

Description

technical field [0001] The invention relates to the technical field of electronic equipment, in particular to a multi-channel LVDS clock line detection method and system. Background technique [0002] In the connection between the display screen and the driver board, LVDS (Low Voltage Differential Signaling, low voltage differential signal) is the most commonly used standard. In order to transmit full high-definition signals, LVDS is extended from one channel to multiple channels, and each channel of LVDS signal has a A pair of clock signals and three to six pairs of data signals. Due to the large number of interface connections and the small spacing between the connection pins of the LVDS signal line, it is prone to defects such as virtual soldering and tin connection. When producing these driver circuit boards in the factory, it is necessary to test the connectivity of LVDS and other lines. [0003] The traditional multi-channel LVDS clock line test method is to use the ...

AI Technical Summary

Problems solved by technology

Since some displays use the LVDS clocks of each channel to collect the corresponding data, when the unsampled clock lines are soldered or soldered, the image of the display may be abnormal.

The traditional multi-channel LVDS clock line test method has the disadvantage of low detection reliability

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