Circuit and method for suppressing negative voltage of bit line under high power supply voltage

Abstract

The invention relates to the field of the electronic technology, in particular to a circuit for inhibiting a negative bit line under high supply voltage. The circuit comprises N SRAM (Static Random Access Memory) storage units, a detection unit and a control unit, wherein each SRAM storage unit is connected with a first bit line, a second bit line and a corresponding word line, and carries out a write operation on the corresponding SRAM storage unit when one word line is selected; the detection unit is used for detecting the power voltage of each SRAM storage unit, and generates a regulation signal according to the change of the power voltage; and the control unit is connected with the detection unit, and is regulated by the regulation signal to enable negative voltage obtained by coupling on a first bit line or a second bit line to be grounded when the power voltage exceeds a threshold value. By use of the circuit, through regulation, the negative voltage obtained by coupling on the first bit line or the second bit line is grounded when the power voltage rises, the damage of the gate oxide of a MOS (Metal Oxide Semiconductor) transistor on a bit line passage is avoided, the inhibition of the negative bit line during high voltage is realized, a circuit is simple, and the area of the circuit is saved.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a static random access memory. Background technique [0002] The most common structure of SRAM is as figure 1 As shown, the SRAM storage unit composed of six transistors has a circuit principle: when the voltage of node N1 is high and the voltage of node N0 is low, the value stored in the storage unit is called logic 1, otherwise it is logic 0. When it is necessary to rewrite the data stored in the SRAM storage unit, for example, rewrite the stored value 1 to 0, the corresponding operation steps are: first, charge the word line WL (WordLine) to a high voltage (generally equal to the power supply voltage Vdd), and turn the bit The voltage of the line BL (BitLine) is pulled down from the power supply voltage Vdd to the ground voltage VSS, while the voltage of the reverse bit line BLB is maintained at the power supply voltage Vdd; since the driving ability of the PMOS transisto...

AI Technical Summary

Problems solved by technology

[0005] However, the use of bit line negative voltage technology will cause the gate oxide layer of the MOS transistor on the SRAM bit line path to withstand a large voltage difference when the power supply voltage is high, which may cause breakdown or leakage of the gate oxide layer

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