LDPC encoder of secondary full parallel input cycle left shift in DTMB

Abstract

The present invention provides a LDPC encoder of secondary full parallel input cycle left shift in a DTMB. The encoder comprises a multiplier of a sparse matrix and a vector and a multiplier of a vector and a high-density matrix. The multiplier of the sparse matrix and the vector realizes the multiplication of the sparse matrix and the vector, and the multiplier of the vector and the high-density matrix employs full parallel input cycle left shift mechanism so as to realize the multiplication of the vector and the high-density matrix. The whole encoding process is divided into 2-level streamlines. The 4 / 5 code rate QC-LDPC (Quasi-Cyclic LDPC) encoder in the DTMB system is high in work efficiency and large in throughput, etc.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a QC-LDPC coder with two-level fully parallel input cyclic left shift in a DTMB system. Background technique [0002] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) code is one of efficient channel coding techniques, and Quasi-Cyclic LDPC (QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] The communication system usual...

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Problems solved by technology

[0006] The existing all-parallel input solution of the 4 / 5 code rate QC-LDPC encoder in the DTMB standard is as follows: figure 1 As shown, the main disadvantage of this scheme is that the modulo 2 adder has e×b input terminals, and the delay of the addition operation is long, which will cause the encoder to have low operating frequency and low throughput

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