Method and system for measuring clock synchronization based on double buffer areas

A technology of clock synchronization and measurement method, applied in general control system, control/adjustment system, radio-controlled timer, etc., can solve the problems of frequent time synchronization, insufficient measurement accuracy, low efficiency, etc., and achieve easy execution and data transmission Fast and stable, the effect of improving equipment operation efficiency

CN106444352AActive Publication Date: 2017-02-22青岛大豪信息技术有限公司
9 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2017-02-22

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention provides a method and a system for measuring clock synchronization based on double buffer areas. The system comprises a DSP (digital signal processor) and an FPGA (field programmable gate array), wherein the DSP and the FPGA are arranged in a measuring device; the DSP comprises a data receiving unit, a data calculating unit, a first buffer area and a second buffer area; the data receiving unit is used for receiving sampling data from the FPGA in the measuring device; one of the first buffer area and the second buffer area is used for storing the current sampling data at any time; when the sampling data received by the DSP is the last packet in an absolute time tag TPa, the currently received sampling data is switched to be stored into the other buffer area; when the data length in the other buffer area reaches the measuring and calculating data length TPm, the data calculating unit starts to read the data in the buffer area and calculate parameters, and the original buffer area continues to store the sampling data and calculate the parameters, until the length of the stored sampling data reaches TPm; the original buffer area does not work, and the buffer areas are switched to work, so as to realize the synchronization measuring and calculation.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to the technical field of synchronization of measuring instruments, in particular to a clock synchronization measurement method and system based on double buffers. Background technique

[0002] Instruments and meters with electrical measurement functions such as power analyzers, power quality analyzers, and online power monitoring devices, in order to ensure that two instruments produce the same results when measuring the same signal, or use multiple instruments at different locations in the same measurement system. When measuring, it must have the function of clock synchronization measurement.

[0003] Accurate clock-synchronized measurement functions have an important impact on measuring instruments in terms of synchronous sampling, power event detection, and power failure analysis. Most of the current synchronization measurement methods use timers with large errors; some GPS timing synchronization measurement methods do not co...

Examples

Embodiment Construction

[0038] In order to better illustrate the present invention, the present invention will be described in detail with a preferred embodiment and with accompanying drawings, specifically as follows:

[0039] Such as figure 1 As shown, the present embodiment provides a kind of clock synchronous measuring system based on double buffer zone, comprises DSP system and FPGA system, and FPGA system comprises several FPGAs that are arranged in different measurement devices, and DSP system comprises several FPGAs that are arranged in different measuring devices. DSP within the measuring device. Among them, FPGA is used for data sampling to obtain sampled data; DSP is used for receiving sampled data from FPGA and performing data calculation.

[0040] Such as figure 2 As shown, each DSP in this embodiment includes: a data receiving unit 201 , a data calculating unit 202 , a first buffer 203 and a second buffer 204 .

[0041] The data receiving unit 201 is used for receiving the sampling ...