Embedded type packaging structure and the manufacturing method thereof

Abstract

The invention provides an embedded type packaging structure, comprising a first dielectric layer, a first conductive pattern layer, a first conductive pole layer, an electronic assembly, a second dielectric layer, a second conductive pattern layer and a second conductive pole layer. The first conductive pattern layer, the first conductive pole layer and the electronic assembly are arranged in the first dielectric layer. One surface of the first conductive pattern layer exposes out of the first surface of the first dielectric layer. One surface of the first conductive pole layer exposes out of the second surface of the first dielectric layer. The second conductive pattern layer and the second conductive pole layer are arranged in the second dielectric layer. One surface of the second conductive pattern layer exposes out of the third surface of the second dielectric layer, and is electrically connected with the first conductive pole that exposes out of the second surface. One surface of the second conductive pole layer exposes out of the fourth surface of the second dielectric layer.

Description

technical field [0001] The invention relates to a packaging structure and a manufacturing method thereof, in particular to an embedded packaging structure and a manufacturing method thereof. Background technique [0002] In today's highly informationized society, the multimedia application market continues to expand rapidly, and the integrated circuit packaging technology is also developing towards the trend of digitalization, networking, regional connection and user-friendly use of electronic devices. In order to meet the above requirements, electronic components must meet the requirements of high-speed processing, multi-function, integrated, small size and light weight, etc., and integrated circuit packaging technology is also developing towards miniaturization and high density. Among them, Ball Grid Array (BGA), Chip-Scale Package (CSP), Flip Chip Package (F / C), Multi-Chip Module (MCM) ) and other high-density integrated circuit packaging technologies have also emerged a...

AI Technical Summary

Problems solved by technology

[0007] The above-mentioned embedded packaging structure 1 has the following technical defects: first, the distances from the center of the electronic components 131, 132 to the second metal layer 15 and the third metal layer 16 are the same, in other words, the embedded packaging structure 1 is A symmetrical structure must be as Figure 1D and Figure 1E As shown, the double-sided build-up process is performed, which will reduce the yield

Additionally, if Figure 1G As shown, it is a blind via plating process, and because of this process, the UBM of electronic components must be limited to copper metal, resulting in insufficient design flexibility

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