Thin-film transistors and producing method thereof
A technology of thin film transistors and manufacturing methods, which is applied in the direction of transistors, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve problems such as complex processes, difficulty in controlling the position offset of the gate layer 20, and low product production rates
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no. 1 example
[0045] As shown in FIG. 3 , it shows a schematic cross-sectional view of the self-aligned spacer region of the thin film transistor according to the first embodiment of the present invention. A buffer layer 52 , an active layer 54 , a gate insulating layer 56 and a gate layer 58 are fabricated sequentially on a substrate 50 . The substrate 50 is preferably a transparent insulating substrate, such as a glass substrate. The buffer layer 52 is preferably a dielectric material layer, such as a silicon oxide layer, and its purpose is to help the active layer 54 to be formed on the substrate 50 . The active layer 54 is preferably a semiconductor silicon layer, such as a polysilicon layer. The gate insulating layer 56 is preferably a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or a combination thereof. The gate layer 58 is preferably a conductive material layer, such as a metal layer and a polysilicon layer.
[0046] The structural features of the thin...
no. 2 example
[0055] As shown in FIG. 4A to FIG. 4C , they are schematic cross-sectional views of the self-aligned spacer regions of the thin film transistor according to the second embodiment of the present invention. The components and structural features of the thin film transistor of the second embodiment are substantially the same as those described in the first embodiment, and the similarities will not be described again. The difference is that the gate insulating layer 56 includes a central region 56a, two shielding regions 56b and two extending regions 56c. Wherein, the extension region 56c is an extension of the shielding region 56b, is exposed on both sides of the bottom of the gate layer 58, and extends to cover the source / drain region 54a. It is characterized in that the thickness of the extension region 56c is much smaller than the thickness of the shielding region 56b, which will not affect the fabrication of the spacer region 54b and the source / drain region 54a.
[0056] Acc...
no. 3 example
[0060] As shown in FIG. 5A to FIG. 5F , they are cross-sectional schematic diagrams showing a method for manufacturing a self-aligned spacer region of a thin film transistor according to a third embodiment of the present invention.
[0061] The manufacturing method of the thin film transistor of the present invention can be applied to the aforementioned first embodiment and the second embodiment, and can be applied to a P-type thin film transistor or an N-type thin film transistor. Taking the thin film transistor of the first embodiment as an example, the method for manufacturing the self-aligned spacer region of the thin film transistor will be described in detail below.
[0062] First, as shown in FIG. 5A , a substrate 50 is provided, and a buffer layer 52 is deposited on the substrate 50 , and then an active layer 54 is formed on the buffer layer 54 . The substrate 50 is preferably a transparent insulating substrate, such as a glass substrate. The buffer layer 52 is prefer...
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Abstract
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