Thin film transistors with self aligned light dosed resource structure and their manufacture

A thin film transistor, lightly doped drain technology, applied in transistors, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as low yield and inability to improve complex processes

Inactive Publication Date: 2007-04-04
TPO DISPLAY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the alignment error (photo misalignment) of the exposure technology and the two-time ion implantation process s

Method used

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  • Thin film transistors with self aligned light dosed resource structure and their manufacture
  • Thin film transistors with self aligned light dosed resource structure and their manufacture
  • Thin film transistors with self aligned light dosed resource structure and their manufacture

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0061] As shown in FIG. 3 , it shows a schematic cross-sectional view of the self-aligned LDD structure of the thin film transistor according to the first embodiment of the present invention. A buffer layer 52 , an effective layer 54 , a gate insulating layer 56 and a gate layer 58 are sequentially fabricated on a substrate 50 . The substrate 50 is preferably a transparent insulating substrate, such as a glass substrate. The buffer layer 52 is preferably a dielectric material layer, such as a silicon oxide layer, and its purpose is to help the effective layer 54 to be formed on the substrate 50 . The active layer 54 is preferably a semiconductor silicon layer, such as a polysilicon layer. The gate insulating layer 56 is preferably a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or a combination thereof. The gate layer 58 is preferably a conductive material layer, such as a metal layer and a polysilicon layer.

[0062] The structural features of th...

no. 2 example

[0070] As shown in FIG. 4A and FIG. 4B , they are schematic cross-sectional views of the self-aligned LDD structure of the thin film transistor according to the second embodiment of the present invention. The components and structural features of the thin film transistor of the second embodiment are substantially the same as those described in the first embodiment, and the similarities will not be described again. The difference is that the gate insulating layer 56 of the second embodiment is composed of a first insulating layer 55 and a second insulating layer 57, wherein the first insulating layer 55 is preferably a silicon oxide layer, a A silicon nitride layer, a silicon oxynitride layer or a combination thereof, the second insulating layer 57 is preferably a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or a combination thereof.

[0071] A central region 56 a , two shielding regions 56 b and two extension regions 56 c are defined on the gate ins...

no. 3 example

[0075] 5A to 5F , which are schematic cross-sectional views showing a method for manufacturing a self-aligned LDD structure of a thin film transistor according to a third embodiment of the present invention.

[0076] The manufacturing method of the thin film transistor of the present invention can be applied to a P-type thin film transistor or an N-type thin film transistor. The following takes the thin film transistor of the first embodiment as an example to describe the manufacturing method of the self-aligned LDD structure in detail.

[0077] First, as shown in FIG. 5A , a substrate 50 is provided, and a buffer layer 52 is deposited on the substrate 50 , and then an effective layer 54 is formed on the buffer layer 54 . The substrate 50 is preferably a transparent insulating substrate, such as a glass substrate. The buffer layer 52 is preferably a dielectric material layer, such as a silicon oxide layer, and its purpose is to help the effective layer 54 to be formed on the ...

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Abstract

In the thin film transistor, an active layer includes a channel region, a first doped region, and second doped region. Insulation layer of grid pole formed on the active layer includes at least a central region, a shelter region and an extended region. The central region covers the channel region. The shelter region positioned at periphery of the central region covers first doped region. The extended region is positioned at periphery of the shelter region covers second doped region. A grid layer is formed on grid insulation layer. The grid layer covering the central region exposes the shelter region and the extended region. Thickness of the shelter region of grid insulation layer is thicker than thickness of the extended region of grid insulation layer.

Description

technical field [0001] The invention relates to a thin film transistor technology, in particular to a lightly doped drain structure of a polysilicon thin film transistor and a manufacturing method thereof. Background technique [0002] A thin film transistor (TFT) of a liquid crystal display (hereinafter referred to as LCD) is used as a switching element of a pixel, and generally can be divided into two types: an amorphous silicon TFT and a polysilicon TFT. Due to the higher carrier mobility of polysilicon TFTs, better integration of driving circuits, and smaller leakage currents, polysilicon TFTs are more commonly used in circuits with high operating speeds, such as: static random access memory (static random access memory, SRAM). However, the polysilicon TFT is prone to leakage current in the off state, which will cause the LCD to lose charge or consume the backup power of the SRAM. In order to solve this problem, a lightly doped drain (LDD) structure is currently used t...

Claims

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Application Information

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IPC IPC(8): H01L29/786H01L21/336
Inventor 张世昌方俊雄邓德华蔡耀铭
Owner TPO DISPLAY
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