CIC filter design method based on parallel computation

A filter design, filter technology, applied in impedance networks, digital technology networks, electrical components, etc., can solve problems such as processing speed limitations, and achieve the effect of ensuring system operation

Inactive Publication Date: 2017-02-22
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This is the limitation of the processing speed of the t

Method used

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  • CIC filter design method based on parallel computation
  • CIC filter design method based on parallel computation
  • CIC filter design method based on parallel computation

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0067] Example 1

[0068] In Embodiment 1, the operation results of a single-stage parallel CIC filter and a traditional single-stage serial CIC filter are compared.

[0069] Suppose the sampling frequency of the input signal is f s = 1GHz. The operating frequency of the traditional single-stage serial CIC needs to be at f s =1GHz. In the parallel CIC design of the present invention, M=4, D=8, and a single-stage CIC filter is equivalent to Q=1. The parallel filter works at f cic = F s / M=250MHz.

[0070] The design of the single-stage parallel CIC filter in Embodiment 1 includes the following steps:

[0071] ①For the sampling rate f s =1GHz input signal S i ,0≤i≤N (where N is the fixed data length). We design the filter working frequency as f cic =250MHz, the number of parallels is M=4. Determine the number of samples D=8;

[0072] ② Divide it into groups of 4 data, and divide the signal flow S i ,0≤i≤N becomes the following formula:

[0073] {(S 0 ,S 1 ,...,S 3 ),(S 4 ,S 5 ,...,S...

Example Embodiment

[0084] Example 2

[0085] In Embodiment 2, the operation results of the multi-stage parallel CIC filter and the traditional multi-stage serial CIC filter are compared.

[0086] Suppose the sampling frequency of the input signal is f s = 1GHz. The operating frequency of the traditional single-stage serial CIC needs to be at f s =1GHz. In the parallel CIC design of the present invention, M=4, D=8, and a single-stage CIC filter is equivalent to Q=1. The parallel filter works at f cic = F s / M=250MHz.

[0087] The design of the multi-stage parallel CIC filter in Embodiment 2 includes the following steps:

[0088] ①For the sampling rate f s =1GHz input signal S i ,0≤i≤N (where N is the fixed data length). We design the filter working frequency as f cic =250MHz, the number of parallels is M=4. Determine the number of samples D=8;

[0089] ② Divide it into groups of 4 data, and divide the signal flow S i ,0≤i≤N becomes the following formula:

[0090] {(S 0 ,S 1 ,...,S 3 ),(S 4 ,S 5 ,...,...

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Abstract

The invention belongs to the field of high speed signal processing, and mainly relates to the design of a CIC filter based on parallel computation so as to improve the signal processing speed and the operation stability. The aim of the invention is to provide a CIC filter design method based on parallel computation and perform hardware implementation on the same. According to the CIC filter design method provided by the invention, a to-be-processed signal data stream Si is divided according to sections, i is not smaller than 0 and is not greater than N (N is a data length and can be an infinite length), and each section contains M data. Meanwhile reordered M paths of data are operated to operate the group of data within K1 time. The entire system works in a stream line manner, thereby being able to continuously work, and a group of M data is output within each clock. Finally, D-fold extraction is performed on the output data to obtain a subsequently expected extraction postprocessing speed. The parallel CIC filter herein works on a fcic speed, thereby improving the processing speed of the entire system.

Description

technical field [0001] The invention belongs to the field of high-speed signal processing, and mainly relates to the design of a CIC filter based on parallel operation, which improves signal processing speed and ensures operation stability. Background technique [0002] In the application of digital signal processing, as the sampling rate increases, the rate of the sampled data flow becomes correspondingly high. As a result, the speed of subsequent signal processing cannot keep up, and even high-speed digital signal processing devices such as FPGA are very difficult. The single signal we process is often a narrowband signal relative to the sampling rate. At this time, we can reduce the signal rate before processing. This reduction in data sampling rate can be achieved by post-decimation with a CIC filter. In the software radio, the CIC filter has been widely used as the decimation or interpolation filter function after the digital up-down conversion. [0003] CIC filter,...

Claims

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Application Information

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IPC IPC(8): H03H17/00
CPCH03H17/00H03H2017/0081
Inventor 黄文龙袁晓垒甘露廖红舒
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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