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Thread Waiting in Multithreaded Processor Architecture

A thread and processing core technology, applied in the field of processor architecture, can solve problems such as waste of execution resources, waste of processing core resources, delay, etc.

Active Publication Date: 2019-04-16
GOOGLE LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although busy polling of memory addresses can generate beneficial latency by avoiding context switch overhead, it inevitably results in wasted execution resources
For example, with a single-threaded processing core or a hyperthreaded processing core without any hardware thread switching capability, the processing core may become unused for actual work during busy polling, which may waste resources from other hyperthreads on the processing core
Also, if the number of memory addresses being polled is large, this can cause additional delays

Method used

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  • Thread Waiting in Multithreaded Processor Architecture
  • Thread Waiting in Multithreaded Processor Architecture
  • Thread Waiting in Multithreaded Processor Architecture

Examples

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Embodiment Construction

[0017] figure 1 is a block diagram of an example multithreaded processing system 100 . Multi-threaded processing system 100 may execute multiple threads concurrently. Waiting threads can execute atomic memory transactions during the waiting period and can be quickly reactivated for execution by other threads or devices.

[0018] Multithreaded processing system 100 includes processor 102 . Processor 102 may be a physical or logical processing core configured to execute computer program instructions. Processor 102 is coupled to main memory 104 (eg, one or more random access memory (RAM) chips) via interconnect 106 . Interconnect 106 may include a shared system bus or a point-to-point network in various topologies.

[0019] In some implementations, multithreaded processing system 100 includes one or more other processors 108 coupled to main memory 104 via interconnect 106 . Processor 108 may be a physical or logical processing core. Processor 102 and processor 108 may have ...

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Abstract

Methods, systems, and devices for thread waiting, including computer programs encoding on computer storage media.One of the methods includes: the first thread on the processing nucleus starts the task by starting multiple task instructions; the upper thread uses the transactional memory system to initiate the atomic memory affairs, including the designated use of the transactional memory system for designated useAt least the first memory address of the atomic memory transactions, and temporarily stop the task by not continuing the task instructions; as a second -threaded access to the result of the first memory address for the atomic memory transaction, the signal is received by the frontline; and the signal of the frontline; andAs a result of receiving signals, the task instructions are recovered by the frontline and the task instructions are continued.

Description

technical field [0001] This specification refers to processor architectures. Background technique [0002] Some processor architectures can execute multiple independent threads, such as multithreading. In some cases, it is desirable to have a thread wait for an input / output (IO) or synchronous operation rather than yielding the thread to a processor core by context switching another thread on the processor core. To achieve this, software can implement busy polling or spin polling, such as spinlock based synchronization, on one or more memory addresses. Although busy polling of memory addresses can generate beneficial latency by avoiding context switch overhead, it inevitably results in wasted execution resources. For example, with a single-threaded processing core or a hyperthreaded processing core without any hardware thread switching capability, the processing core may become unused for actual work during busy polling, which may waste resources of other hyperthreads on t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
CPCG06F9/3834G06F9/3851G06F13/24G06F9/467G06F12/0842G06F12/0813
Inventor B.C.塞雷布林
Owner GOOGLE LLC
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