Method for forming iii-v family channels

Abstract

Embodiments of the present disclosure relate to semiconductor devices, such as transistors, for amplifying or switching electronic signals. In one embodiment, a first trench is formed in the dielectric layer formed on the substrate to expose the surface of the substrate; a multi-stacked layer structure is formed in the first trench; and a second semiconductor compound layer A third semiconductor compound layer is formed on the dielectric layer, wherein the second semiconductor compound layer has an etch resistance lower than that of the first and third semiconductor compound layers against etchant; a second semiconductor compound layer is formed in the dielectric layer. trenches to partially expose at least the second semiconductor compound layer and the third semiconductor compound layer; and selectively removing the second semiconductor compound layer so that the first semiconductor compound layer is separated from the third semiconductor compound layer by voids isolation.

Description

technical field [0001] Embodiments of the disclosure generally relate to circuit devices and fabrication of circuit devices. Background technique [0002] The scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) has enabled continued improvements in speed performance, density, and cost per unit function of integrated circuits. The semiconductor industry is also in the midst of a transition from typically planar two-dimensional transistors to three-dimensional transistors using three-dimensional gate structures. In a three-dimensional gate structure, the channel, source, and drain are raised from the silicon substrate, and the gate wraps around three sides of the channel. One type of three-dimensional transistor of this type is known as a FinFET (Fin Field Effect Transistor), where the channel connecting the source and drain is a thin "fin" jut from the substrate. The gate has greater control over charge-carrying in the channel because the gate extends ov...

AI Technical Summary

Problems solved by technology

However, in practice, neither of these buffer and barrier layers can completely prevent the propagation of dislocations and stacking faults into III-V epitaxial layers.

In addition, it has also been observed that a leakage path from the source to the drain of the transistor may develop in the blocking and / or buffer layers, resulting in increased off-state leakage current and degradation of the transistor's ability to fully turn off

As a result, the performance of the transistor deteriorates

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