Fractional n-type PLL circuit

Abstract

A fractional-N phase locked loop (PLL) circuit (104, 600, 800) is provided. The PLL circuit (104, 600, 800) generates a spread spectrum clock (SSC) using averaging techniques to suppress phase interpolator nonlinearities. The PLL circuit (600, 800) includes a fractional frequency divider (606, 806) with hybrid finite impulse response (FIR) filtering. Furthermore, a small and low power frequency divider for a hybrid FIR fractional N-type PLL circuit (600, 800) is provided.

Description

technical field [0001] Embodiments of the present invention relate to the field of electronic circuits, in particular to a fractional frequency divider type fractional N phase locked loop for a spread spectrum clock generator. Background technique [0002] A spread spectrum clock (Spread Spectrum Clock, SSC) signal is used in electronic components to facilitate suppression of electromagnetic interference. The SSC signal is clocked with different frequencies, typically oscillating between min / max, depending on the desired modulation shape function (eg, sine wave, triangle wave, etc.). The SSC signal can be generated by modulating the frequency of a clock signal generated by a Phase Locked Loop circuit (Phase Locked Loop, PLL) according to a predetermined modulation frequency and modulation angle. A sigma-delta modulator type fractional-N PLL can be used to generate the SSC signal; however, the quantization noise of the sigma-delta modulator will cause jitter on the PLL outpu...

AI Technical Summary

Problems solved by technology

A sigma-delta modulator type fractional-N PLL can be used to generate the SSC signal; however, the quantization noise of the sigma-delta modulator can cause jitter on the PLL output

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