A ftl optimization method based on block group structure

Abstract

The invention discloses an FTL optimization method based on a block group structure. The method comprises the following steps: forming a block group in a flash memory architecture by using several blocks, and correspondingly allocating the reserved space to each block group; establishing address mapping based on the block group, wherein the first mapping is global mapping, the second mapping is a local mapping table, each block group maintains a local mapping to preserve the mapping relationship between the logical offset and the physical offset in the corresponding block group; and after completing a write operation, triggering garbage collection if the ratio of free pages in the block group which currently implements the write operation to the entire block group is smaller than a threshold value. By adopting the FTL optimization method disclosed by the invention, based on a page-level address mapping scheme of the block group structure, the problem of large particle size of collected garbage in an address mapping scheme based on block groups can be solved by making full use of the reserved space and the inter-channel parallelism of a flash memory device, and the consumption of metadata on the cache can be reduced by using the locality of the block groups.

Description

technical field [0001] The invention belongs to the field of solid-state storage devices, and in particular relates to an optimization method for a flash conversion layer, and is particularly suitable for optimizing a conversion layer based on NAND Flash. Background technique [0002] Flash memory is abbreviated as Flash in English, and its full name is Flash Memory. NAND-type flash memory is a major non-volatile flash memory technology. NAND Flash storage media has the characteristics of high density, large capacity, and non-volatility. Compared with magnetic media, it has lower read and write latency and energy consumption. According to the different levels of the voltage of the internal storage data unit, that is, in a single flash memory unit, whether to store one bit of data or multiple bits of data, it can be divided into SLC (Single Level Cell, single-layer unit) type and MLC (Multi Level Cell, multi-layer unit) type. [0003] Although NAND-type flash memory has g...

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[0013] Although the three-level page-level mapping proposed in the above scheme reduces the size of the traditional page-level mapping mapping table, it does not consider the memory consumption of metadata other than the mapping table, and because continuous logical pages are allocated in different In the block group, the three-tier page-level mapping scheme still needs to cache a large amount of metadata in order to maintain the normal operation of the scheme

At the same time, the three-level page-level solution needs to process the entire block group during garbage collection. Even if the multi-level parallelism of flash memory is used, it will occupy the entire channel during garbage collection, so the garbage collection of the three-level page-level mapping will have a negative impact on performance. great influence

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