Shifting register, GOA circuit, driving method thereof and display device

A technology of shift register and potential, applied in the fields of GOA circuit and its driving method, shift register, and display device, to achieve the effects of saving layout space, stable output, and increasing anti-noise ability

Active Publication Date: 2017-05-17
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention aims at the problem that the stability and low power consumption of the existing GOA driving ci

Method used

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  • Shifting register, GOA circuit, driving method thereof and display device
  • Shifting register, GOA circuit, driving method thereof and display device
  • Shifting register, GOA circuit, driving method thereof and display device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] This embodiment provides a shift register, such as figure 1 As shown, it includes: a plurality of input modules 1, a plurality of output modules 2, a first reset module 3 corresponding to each input module 1, a first noise reduction module 4, a second noise reduction module 5, and a second reset module 6.

[0045] Wherein, in this embodiment, two input modules 1 and two output modules 2 are used for illustration, and the case of three or more input modules 1 and output modules 2 is similar to this embodiment.

[0046] Each input module 1 is connected to the pull-up node PU and its corresponding signal input terminals Input1 and Input2, and is used to charge the pull-up node PU under the control of the signal input by the signal input terminal;

[0047]Each output module 2 is connected to the pull-up node PU, the signal output terminals OUT1 and OUT2 corresponding to each, the first clock control signal terminals CK1 and CK2 corresponding to each, and the first reset mo...

Embodiment 2

[0055] This embodiment provides a shift register, such as figure 2 As shown, it includes: two input modules 1, two output modules 2, a first reset module 3 corresponding to each input module 1, a first noise reduction module 4, a second noise reduction module 5, and a second reset module 6.

[0056] in, figure 2 The upper left is the first input module 1, the lower left is the second input module 1, the upper middle is the first output module 2, and the upper right is the second output module 2.

[0057] The shift register of this embodiment has four clock control signal terminals CK1, CK2, CK3, and CK4, wherein CK1, CK2, CK3, and CK4 are clock signals with a difference of 1 / 4 cycle in sequence.

[0058] Each input module 1 includes a first transistor, the control electrode and the first stage of the first transistor are connected to the signal input terminal Input1 corresponding to the input module 1 , and the second stage of the first transistor is connected to the pull-...

Embodiment 3

[0077] This embodiment provides a GOA circuit, including a plurality of cascaded shift registers of the foregoing embodiments.

[0078] GOA cascade see image 3 , Odd-numbered shift registers, such as 1-stage shift registers are controlled by CK1, CK2, CK4 clock control signal terminals; even-numbered stage shift registers, such as 2-stage shift registers are controlled by CK3, CK4, CK2 clock control signal terminals ;So on and so forth. figure 2 Among them, Input1 is the output signal N-1 of the upper stage, and Input2 is the signal N+2 output by the lower stage. Out1 is the first output signal N of the current stage, and Out2 is the second output signal N+1 of the current stage.

[0079] This embodiment also provides a driving method for the above-mentioned GOA circuit, see Figure 4 , the method includes:

[0080] In the first stage t1, the first input module 1 charges the pull-up node PU under the control of the signal input from the first signal input terminal Input1...

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PUM

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Abstract

The invention provides a shifting register, a GOA circuit, a driving method thereof and a display device, belonging to the technical field of display. The invention aims to solve the problem of further prompting the low stability and low power consumption of the present GOA circuit. The shifting register comprises a plurality of input modules, a plurality of output modules, a first noise reduction module and a second noise reduction module, wherein the shifting register has a plurality of output control points due to the existence of the plurality of input modules, so that the switch-on/off of multiple rows of grid lines can be controlled, the driving control capability of a single-pole shifting register can be promoted and the configuration space of the shifting register can be effectively saved; besides, the output modules respectively control the pull-down nodes through the feedback of the noise reduction modules, so that the anti-noise capability of the circuit can be obviously increased and the output is relatively smooth; the panel yield is greatly increased; the shifting register provided by the invention is suitable for various display devices.

Description

technical field [0001] The invention belongs to the field of display technology, and in particular relates to a shift register, a GOA circuit, a driving method thereof, and a display device. Background technique [0002] The gate driver on array (Gate Driver on Array, GOA) driving circuit of the array substrate utilizes the liquid crystal display array manufacturing process to manufacture the gate scanning driving signal circuit on the array substrate to realize the progressive driving and scanning of the pixel units. The GOA drive circuit can not only reduce the welding process of external integrated circuits, improve the integration level, but also increase production capacity and reduce production costs. It is the first choice for small and medium-sized liquid crystal display products (such as mobile phones). [0003] The inventors have found that there are at least the following problems in the prior art: in recent years, with the increasing size of LCD panels, the degre...

Claims

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Application Information

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IPC IPC(8): G09G3/36G11C19/28
CPCG09G3/3611G09G2310/0286G11C19/28G09G3/3677G09G2300/0408G09G2310/061H04M1/0266
Inventor 王继国
Owner BOE TECH GRP CO LTD
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