Semiconductor structure and fabricating method thereof

Abstract

A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have a first height, and a first epitaxy structure is disposed in the first fin structure, which a portion of the first epitaxy structure is above the first fin spacers and having a first width. In the test region, second fin spacers cover sidewalls of the second fin structure and have a second height, and the second height is greater than the first height. A second epitaxy structure is disposed in the second fin structure, and a portion of the second epitaxy structure is above the second fin spacers and having a second width, which the second width is less than the first width.

Description

technical field [0001] Embodiments of the present invention relate to integrated circuit devices, and more particularly, to semiconductor structures and methods of fabrication thereof. Background technique [0002] The manufacture of integrated circuits (ICs) has been greatly driven by the need to increase the density of integrated circuits formed in semiconductor devices. This is usually done by enforcing more aggressive design rules to allow greater density of formed IC devices. However, the increased density of IC devices such as transistors has also increased the complexity of handling semiconductor devices with reduced feature sizes. [0003] For example, semiconductor devices such as Fin Field Effect Transistors (FinFETs) have been scaled down through various technology nodes, using epitaxial (epi) semiconductor materials have achieved strained source / drain features (e.g., stressor regions) for enhanced current carrying ion mobility and improve device performance. F...

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Problems solved by technology

However, the increased density of IC devices such as transistors has also incre

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