Multi-processor system and clock synchronization method

Abstract

Embodiments of the invention relate to a multi-processor system and a clock synchronization method. The method comprises the steps of when a slave processor subjected to hot plugging is detected by a master processor, if a high level of a TSC synchronous pin is effective, enabling the TSC synchronous pins of all the processors, and sending an indication signal to a first programmable logic device, wherein the indication signal is used for indicating the first programmable logic device to generate a high pulse starting from a low level and greater than a preset time length at falling edges of a first number of bus clocks; sampling count values of a TSC counter through rising edges of internal synchronous clocks after the master processor and each slave processor detect that the high pulse reaches the TSC synchronous pins of the master processor and each slave processor; and enabling each slave processor and the master processor to perform TSC clock synchronization according to the count values, sampled by each slave processor and the master processor, of the TSC counter. According to the system and the method, the master processor is matched with the programmable logic device, so that the success rate of the TSC clock synchronization can be increased.

Description

technical field [0001] The invention relates to the computer field, in particular to a multiprocessor system and a clock synchronization method. Background technique [0002] At present, multi-processor systems are relatively common. In multi-processor systems, clocks are required to synchronize the time between threads. At present, there are two mainstream core clocks for X86 servers: timestamp timer ( time stamp counter (TSC) clock and high precision timer (high precision event timer, HPET) clock. The difference between the two is that the TSC clock is based on a 64-bit hardware counter inside a central processing unit (CPU), while the value of the counter of the HPET clock needs to be read from the memory. When the system works on the HPET clock, in the actual TPC-C database application performance test, it is found that a large amount of CPU time is consumed in processing and reading operations located in the memory clock. After the actual TPC-C test, in the 4P (INTELI...

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Problems solved by technology

[0007] Due to the device delay, cable delay and the delay caused by the rising edge transition caused by the CPU output type being Open Drain (OD) output, the time difference between the rising edge of the TSC waveform reaching each CPU will exceed the time given by Intel. Although the 500ns index of the TSC_SYNC signal can be successfully synchronized with an edge difference of 1us after actual verification, the margin is too small, and there are hidden dangers in stability

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