Formation method of interconnection structure
An interconnect structure and dry etching technology, which is applied in the manufacture of electrical components, circuits, semiconductors/solid-state devices, etc., can solve problems such as holes, affecting the connection performance of interconnect structures, and increasing the difficulty of metal plugs. The effect of electrical connection performance
Active Publication Date: 2017-05-31
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0004] The reduction in the size of the through hole leads to the subsequent filling of the metal material in the through hole and the difficulty of forming a metal plug. Holes often appear in the metal plug formed by the prior art, which affects the connection performance of the interconnection structure
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[0028] As mentioned in the background art, the performance of the interconnect structure formed in the prior art needs to be further improved.
[0029] In an embodiment of the present invention, a method for forming an interconnection structure is provided. The width of the top of the formed second through hole is greater than the width of the bottom, which is beneficial to filling the metal layer in the second through hole, thereby improving the formed interconnection structure. connection performance.
[0030] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0031] Please refer to figure 1 , a substrate 100 is provided, and a dielectric layer 200 is formed on the substrate 100 .
[0032] The substrate 100 may be a semiconductor material including silicon, germanium, silicon germanium or ga...
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Abstract
Provided is a formation method of an interconnection structure. The formation method of the interconnection structure comprises: providing a substrate; forming a dielectric layer on the surface of the substrate; forming a covering cap layer on the surface of the dielectric layer; forming a mask layer on the surface of the covering cap layer, wherein the mask layer exposes a part of the surface of the covering cap layer; etching the covering cap layer to the surface of the dielectric layer by regarding the mask layer as the mask, and forming openings in the covering cap layer; etching sidewalls of the mask layer, and exposing a part of the surface of the covering cap layer; etching the dielectric layer with a part of thickness along the openings in the covering cap layer to form first through holes; performing oxidation treatment on a part of the covering cap layer which is not covered by the mask layer at the sidewalls of the openings to form an oxidation layer; etching the dielectric layer to the surface of the substrate along the first through holes to form second through holes, wherein the top width of the second through holes is greater than the bottom width; and forming a metal layer filling the second through holes. According to the method, the performance of the formed interconnection structure can be improved.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming an interconnection structure. Background technique [0002] With the continuous development of semiconductor process technology, such as the introduction of high-K gate dielectric layer, stress engineering technology, pocket ion implantation, and continuous optimization of materials and device structures, the size of semiconductor devices is constantly shrinking, and the spacing between adjacent semiconductor devices is also increasing. Getting smaller and smaller. [0003] In the integrated circuit manufacturing process, after forming the semiconductor device structure on the substrate, it is necessary to use multiple metallization layers to connect each semiconductor device together to form a circuit. The metallization layer includes interconnection lines and contacts formed in contact holes. Metal plugs, the metal plugs in the interconnection holes...
Claims
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IPC IPC(8): H01L21/768
CPCH01L21/76802H01L21/76804H01L21/76816
Inventor 周鸣李小雨
Owner SEMICON MFG INT (SHANGHAI) CORP