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Test structure and method for monitoring probe mark offset by using same

A test structure and probe technology, applied in semiconductor/solid-state device test/measurement, electronic circuit test, electrical measurement, etc., can solve problems such as no system control, failure to find problems in time, human judgment differences, etc. The method is simple Ease of operation, low cost, and the effect of reducing errors

Active Publication Date: 2017-05-31
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

All the inspections of needle mark positions are done manually, there are differences in human judgment, there is no system control, and problems cannot be found in time

Method used

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  • Test structure and method for monitoring probe mark offset by using same
  • Test structure and method for monitoring probe mark offset by using same
  • Test structure and method for monitoring probe mark offset by using same

Examples

Experimental program
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Effect test

Embodiment 1

[0035] This embodiment provides a test structure, which is applied to Wafer Acceptance Test (WAT for short), the test structure is set in the wafer, the wafer includes multiple metal layers, the test structure includes a plurality of metal solder plate and a plurality of active devices, and one active device is arranged under a metal pad to form a CUP (Circuit UnderPad, that is, a circuit is placed under the pad) structure;

[0036] Among them, the gates of all active devices in the CUP structure are connected in parallel to a first pad through a first connection line, the source is connected in parallel to a second pad through a second connection line, and the drain is connected to a second pad through a third connection line. The lines are connected in parallel to a third pad, and the substrate is connected in parallel to a fourth pad through the fourth connection line.

[0037] Specifically, refer to figure 1 A top view of a CUP structure and figure 2 As shown in the enl...

Embodiment 2

[0047] This embodiment provides a system and method for monitoring the deviation of the probe needle mark including the above-mentioned testing mechanism, and the system also includes:

[0048] A plurality of probes are in contact with the first to fourth pads respectively, and are used to measure the saturation current of the active devices connected in parallel;

[0049] The monitoring and statistics unit is connected with the plurality of probes, and is used for receiving and judging the needle mark deviation of the probes according to the saturation current.

[0050] As a preferred implementation manner, in this embodiment, an NMOS transistor is also taken as an example for description. The monitoring and statistics unit is a statistical process control system (SPC system). Through the SPC system, the saturation current (IDS) of parallel active devices can be monitored in real time, and the needle mark deviation of the probe can be judged in real time through the monitore...

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Abstract

The invention relates to the technical field of integrated circuit testing, particularly to a test structure and a method for monitoring probe mark offset by using the same. According to the test structure disclosed by the invention, a novel test structure is introduced to conventional WAT (wafer acceptance test); the number N (N is greater than or equal to 4) of metal bond pads is consistent to the number of monitored probe clamping pins; an active device is put below each metal bond pad; gates, sources and drains of the N (N is greater than or equal to 4) active devices, and a substrate are connected in parallel to be connected to four different bond pads respectively; and by measuring saturation current of the active devices in different positions below the bond pads, the offset condition of the probe pins can be monitored in real time.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a testing structure and a method for monitoring the deflection of probe marks by using the testing structure. Background technique [0002] With the pursuit of low unit area cost of integrated circuits and the need for special functional structures, CUP (circuit under pad, that is, placing circuits under pads) structure designs gradually emerged. The structural design is to place active devices such as MOS transistors under the bond pad to achieve the purpose of saving area. A common practice is to place ESD circuits (ie, electrostatic protection circuits) on IO pads (ie, input and output pads). To improve chip integration. For this structure, due to the stress generated by needle sticking or bonding during testing, it is easy to cause the electrical parameters of the CUP (such as threshold voltage, saturation leakage current) to drift, which will lead to poor...

Claims

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Application Information

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IPC IPC(8): H01L23/544G01R31/28
CPCH01L22/30G01R31/2884G01R31/2891H01L22/34
Inventor 赵毅瞿奇陈玉立彭飞梁卉荣
Owner WUHAN XINXIN SEMICON MFG CO LTD