Assertion-Based Memory Controller Interface Timing Parameterized Verification System

Abstract

The invention provides an assertion-based parameterization verification system of an interface time sequence of a storage controller and relates to the technical field of verification of integrated circuits. The system comprises a configuration unit, a control unit, an assertion document library, a storage controller to be verified and a detection unit, wherein the configuration unit is used for transmitting configuration parameters to the assertion document library; the control unit is used for transmitting control parameters to the assertion document library; the assertion document library is used for selecting assertion documents needed by verification according to values of the configuration parameters and the control parameters, verifying the needed assertion document, matching an interface signal time sequence with an interface signal time sequence requirement, generating matching information and transmitting the matching information to the detection unit; the storage controller to be verified is used for transmitting the interface signal time sequence to the assertion documents needed by verification and modifying the interface signal time sequence according to failure matching information; the detection unit is used for transmitting the failure matching information to the storage controller to be verified when detecting a matching failure signal. Through the assertion-based parameterization verification system of the interface time sequence of the storage controller, plenty of verification time can be reduced; the working difficulty is reduced; and the accuracy of the verification is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit verification, in particular to an assertion-based memory controller interface sequence parameterized verification system. Background technique [0002] As SoC becomes more and more complex, the types of memory used and the complexity of access timing are also increasing, and the time and human resources required for simulation verification are also increasing, which can be completed within the limited project time The urgency of the verification task is increasing. [0003] The traditional verification method for memory timing verification is to capture the memory interface access waveform during the simulation process, and then ensure the correctness of the timing through manual confirmation. [0004] The shortcomings of the above-mentioned existing methods are mainly manifested in: (1) time-consuming, it takes a lot of time to capture the waveform and confirm the timing. (2) Inaccur...

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Problems solved by technology

[0004] The shortcomings of the above-mentioned existing methods are mainly manifested in: (1) time-consuming, it takes a lot of time to capture the waveform and confirm the timing

(2) Inaccurate, human factors cannot guarantee the correctness of timing verification, and it is easy to make mistakes

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