Processing board structure of double interface RAM test equipment
A technology for testing equipment and processing boards, applied in static memory, instruments, etc., can solve problems such as poor applicability, low testing efficiency, and large equipment volume, and achieve the effects of enhanced environmental adaptability, improved testing efficiency, and high reading and writing speeds
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Embodiment 1
[0018] Such as figure 1 Shown, a kind of dual-port RAM test equipment comprises housing 1, display screen 2, main board 3 connected with described display screen 2, processing board 5, SCSI-68 interface 6 connected with processing board 5; Said main board 3 and the processing board 5 are connected through the PCI-E interface 4; the display screen 2, the main board 3, the PCI-E interface 4, the processing board 5, and the SCSI-68 interface 6 are all arranged inside the casing 1.
[0019] Among them, the dual-port RAM data processing board 5 (hereinafter referred to as the processing board 5 ) mainly completes functions such as dual-port RAM read and write timing conversion, docking with the PCI bridge chip, interrupt temporary storage, and store-and-forward.
[0020] The SCSI-68 interface 6 is connected to the device under test through a SCSI cable. One end of the cable adopts a male head of SCSI-68 to facilitate docking with the test device;
Embodiment 2
[0022] On the basis of Example 1, such as figure 2 As shown, the processing board 5 includes a PCI-E bridge chip 7, an FPGA 8, a drive circuit 9, and a power module 10; the PCI-E interface 4 is connected to the FPGA 8 through a PCI-E bridge chip 7; the power module 10 are respectively connected with PCI-E bridge chip 7, FPGA 8, driving circuit 9; Said FPGA 8 is electrically connected with SCSI-68 interface 6 through driving circuit 9.
[0023] Among them, the PCI-E bridge chip 7 is RTL8111E, the read and write speed of this solution is high, and the software and hardware design is relatively complicated. RTL8111E converts PCI-E to Gigabit Ethernet interface, Gigabit Ethernet interface is converted to RGMII interface through 88E1111, and FPGA completes the conversion between RGMII and dual-port RAM;
[0024] There are four kinds of power requirements in the scheme in the embodiment 2 are respectively:
[0025] 1) 5V power supply: provide power to the cable side of the driver...
Embodiment 3
[0032] On the basis of Example 1, such as image 3 As shown, the processing board 5 includes a PCI-E bridge chip 7, a driver circuit 9 connected to the PCI-E bridge chip 7, and a power module 10; the power module 10 is connected to the PCI-E bridge chip 7 and the driver circuit 9 respectively are connected; the driver circuit 9 adopts a dual-power bus driver chip SN74LVC4245A.
[0033] Among them, the PCI-E bridge chip 7 is CH368. The reading and writing speed of this solution is a bit low, but due to the characteristics of CH368, the circuit design and development are relatively simple, and the risk is relatively low. CH368 is a general interface chip connected to PCI-Express bus, supporting I / O port mapping, memory mapping, expansion ROM and interrupt. CH368 converts the high-speed PCIE bus into an easy-to-use 32-bit or 8-bit active parallel interface similar to the ISA bus, which is used to make low-cost computer boards based on the PCIE bus, and to convert boards original...
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