Manufacturing method for semiconductor device

Abstract

The invention provides a manufacturing method for a semiconductor device, and relates to the technical field of semiconductors. The manufacturing method comprise providing a semiconductor substrate, and forming a hard mask layer defining the pattern of a shallow trench isolation structure on the surface of the semiconductor substrate; forming a shallow trench isolation structure in the semiconductor substrate with the surface of the shallow trench isolation structure being lower than that of the hard mask layer and higher than that of the semiconductor substrate; forming a protective layer on the surface of the shallow trench isolation structure through deposition; removing the hard mask layer; and removing the protective layer. According to the invention, by forming the protective layer on the shallow trench isolation structure, the surface of the shallow trench isolation structure can be effectively prevented from being etched and damaged during the wet method etching removal process of the hard mask layer, furthermore the STI step height fluctuation is small, and therefore the performance and the yield rate of the device are increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] In the semiconductor manufacturing process, the performance of the formed shallow trench isolation (STI) structure is critical to the performance and yield of the final formed semiconductor device. [0003] The manufacturing method of existing shallow trench isolation structure comprises the following main steps: as Figures 1A-1B As shown, at first, a buffer layer 101 and a hard mask layer (SiN) 102 are formed on a semiconductor substrate 100, the buffer layer and the hard mask layer are patterned, the semiconductor substrate is etched to form an opening of a shallow trench isolation structure, and then Deposit shallow trench isolation material 103 to fill the opening, and perform CMP to stop on the hard mask layer 102, and then remove the hard mask layer 102 to form a shallow trench isolatio...

AI Technical Summary

Problems solved by technology

[0004] When the size of CMOS devices is reduced to the 28nm node and below, in the manufacturing process of the shallow trench isolation structure, after the hard mask layer SiN in the active region is removed, the step height of the shallow trench isolation structure (STI) (step high ) becomes increasingly difficult to control

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