Processor fault record generation method and apparatus

Abstract

The invention relates to the field of computers, in particular to a processor fault record generation method and apparatus. The processor fault record generation method comprises the steps of obtaining an instruction address in a current program counter (PC) of a processing unit through a JTAG channel when a control chip detects that the processing unit in a CPU stops responding, creating a first class table item comprising the instruction address in the current PC, and recording the first class table item in an instruction address table; and when the number of table items recorded in the instruction address table reaches a preset value, triggering CPU interrupt by the control chip. According to the scheme provided by the method and the apparatus, more information can be provided for processor fault analysis, so that the fault analysis efficiency is improved.

Description

technical field [0001] The present application relates to the field of computers, in particular to a method and device for generating processor fault records. Background technique [0002] The central processing unit (CPU) is the computing core and control core of devices with data processing functions such as computers and servers. A CPU in a device is connected to a memory in the device through a bus, and processes data by interpreting and executing program instructions in the memory. [0003] The existing CPU usually includes an arithmetic logic unit (arithmetic logic unit, ALU), a register (register), a cache memory (Cache), and a data, control, and status bus (bus) for realizing the connection among the three. [0004] In the program run by the CPU, a series of instructions will be executed repeatedly until a preset condition in the program is reached. During actual operation, due to design defects or unforeseen reasons in the actual application environment, the prese...

AI Technical Summary

Problems solved by technology

However, many dead loops that appear in practice are sporadic, or do not appear every time, and it is difficult to reproduce

Therefore, the low efficiency of the existing CPU infinite loop positioning technology has become an urgent problem to be solved in the software product design process.

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