54results about How to "Improve the efficiency of failure analysis" patented technology

A semiconductor structure for testing an MIM (Metal-Insulating medium-Metal) capacitor comprises a plurality of layers, including a first metal layer, a second metal layer, an upper pole-plate and a lower pole-plate; the first metal layer at least comprises a first circuit area and a second circuit area; the second metal layer is arranged under the first metal layer, spaced from the first metal layer through a medium layer and electrically connected with the second circuit area; the upper pole-plate is arranged in the medium layer in a position near the first metal layer and electrically connected with the first circuit area; the lower pole-plate is opposite to the upper pole-plate in the vertical direction, arranged in the medium layer in a position near the second metal layer, spaced from the upper pole-plate through an insulating layer and electrically connected with the second circuit area. The semiconductor structure is formed on a P type semiconductor substrate, and the second metal layer is electrically connected with the P type semiconductor substrate through a first closed circuit, so that a second closed circuit from the upper pole-plate to the P type semiconductor substrate is formed when an electric leakage area exists in the insulating layer; the semiconductor structure can accurately detect whether an electric leakage area exists in the MIM capacitor, is simple to manufacture and low in cost, and is especially suitable for quickly positioning the electric leakage area of a large-area MIM capacitor.

The invention discloses a reason analyzing and locating method for a high resistance grounding fault of a transmission line. The method comprises: obtaining simulated analysis chart of the high resistance grounding faults of the transmission line in different zones by an all-digital real-time simulation APSS system, and comparing with an actual fault oscillograph, wherein the zone corresponding to the highest waveform similarity is the specific zone where the fault is most likely to occur; comparing the typical fault type oscillograph with the actual fault oscillograph to obtain the most possible fault reason. According to the method provided by the invention, the zone where the high resistance grounding fault of the transmission line occurs can be more accurately determined, fault inspection can be performed in a targeted manner, inspection range of line fault inspectors is reduced, and fault inspection time is shortened; reason for the high resistance grounding fault of the transmission line can be more accurately determined, and fault analysis efficiency is improved.

A power grid fault auxiliary analysis system, including a main control module, the main control module is connected to a multi-channel voltage input module, a multi-channel current input module, a multi-channel switch value input module, a large-capacity storage module, a man-machine interface, an external Communication module and grid fault auxiliary analysis system knowledge base; real-time display of three-phase voltage, three-phase current waveform, effective value, cycle, frequency, real-time display of single-phase or three-phase reactive power, active power, and apparent power value; from all Randomly select 1 to 8 AC quantities in the AC analog channel to display their phasor diagrams. The phase of the first phasor is fixed as the reference, and the other phasors are drawn according to the phase relative to the reference phasor, and Display the effective value and phase angle of the phasor. According to the three-phase voltage or three-phase current, the positive sequence, negative sequence, zero sequence effective value and phase angle can be displayed in real time, and it has two harmonic analysis methods.

The invention discloses a method for diagnosing engine faults based on BP neural network, comprising (1) collecting engine fault data and listing the causes of engine faults; (2) determining the optimal hidden layer node number of BP neural network model, and establishing Neural network model; (3) Train the BP neural network model according to the existing fault data; (4) Use the trained BP neural network model to analyze the collected engine data to determine the cause of the fault corresponding to the data. In the past, engine fault diagnosis had defects such as complex mechanism, low detection accuracy, high cost, and failure to display the cause of the fault. The present invention is mainly used in engine fault diagnosis and diagnosis, which is more advantageous than previous methods, saves costs, and improves modeling Efficiency, can quickly lock the optimal number of hidden layer nodes.

The invention provides a method for judging the optical catastrophe type of a semiconductor laser chip, which solves the problems of high judgment cost, long judgment time and low production efficiency of existing semiconductor laser chips COBD and COMD. The method includes: Step 1, setting the loading current; Step 2, loading the loading current on the semiconductor laser chip; Step 3, collecting the current-power curve and current-voltage curve of the semiconductor laser chip; Step 4, if the current-power curve If the current-voltage curve suddenly drops and the current-voltage curve suddenly rises, it is judged that the optical catastrophe of the chip is COMD; if the current-power curve suddenly drops and the current-voltage curve suddenly drops, it is judged that the optical catastrophe of the chip is COBD. The method of the present invention does not require professional equipment, and only needs to collect the current, power value and voltage value in the test process to judge COBD and COMD. The detection equipment is simple and the cost is low, and only ordinary technicians can realize the judgment of failure .

The invention provides a liquid crystal display panel. According to the liquid crystal display panel, each test terminal at the periphery of an array substrate is provided with a switch circuit, when static electricity on the test terminals needs to be released through the switch circuits, all the test terminals are connected with a common electrode wire, and the static electricity is released through the common electrode wire, such that the anti-ESD capability of the test terminals is enhanced, and the service life of the liquid crystal display panel is prolonged.

The invention discloses a failure analysis method, a failure analysis system and network management equipment. Comprehensive network management equipment can obtain positioning information of alarms in a jurisdiction range of transmission network management equipment and positioning information of a first alarm corresponding to the alarms by receiving alarm analysis information reported by various transmission network management equipment; then, when further analyzing, the comprehensive network management equipment is only necessary to perform association analysis of various first alarms, so that a second alarm can be determined; thus, failure positioning is completed; all the alarms are unnecessary to process; alarm data in need of being reported and analyzed is greatly reduced; and thus, the failure analysis efficiency is improved.

The invention discloses a defect point locating method of a semiconductor device, which comprises the following steps: a probe in a defect locator is electrically connected with a device of a semiconductor chip; the device of the semiconductor chip is excited so as to enable a defect point to appear; the probe of the defect locator is used to carve an identification point in a position close to the defect point; and the position relationship between the identification point and the defect point is confirmed. According to the method provided by the invention, when the defect point in the device of the semiconductor chip appears due to excitation, the probe of the existing defect locator is used to set the identification point nearby the defect point, so the defect point can be located according to the position of the identification point and the position relationship between the identification point and the defect point. The method has the advantages that an expensive laser marking machine does not need to be adopted, the cost of failure analysis can be reduced, the existing equipment does not need to be refitted at the same time, the failure analysis can be realized conveniently and rapidly, the simplicity and the practicality are achieved, and the efficiency of the failure analysis is improved.