53results about How to "Improve the efficiency of failure analysis" patented technology

The invention provides a data depth traceability test method. The method comprises the steps of: timely acquiring relevant information of a product to be tested from a server; reading the information acquired from the server by regular expression, performing stored storing on key information in the information, and drawing a yield rate drawing; and according to the yield rate drawing, acquiring the yield rate of the product to be tested, the failure distribution, specific failure information of a failure chip on the product to be tested, and specific information of the chip passing the test on the product to be tested. The key information related to the product to be tested is subject to stored storing by regular expression, the yield rate drawing is drawn, and an engineer can visually know the yield rate and the failure distribution of the product to be tested according to the yield rate drawing; the specific failure information of the failure chip on the product to be tested can be acquired, and the efficiency of failure analysis is improved; and the specific test information of the chip passing the test can be acquired, and the normal data analysis efficiency is improved.

The embodiment of the invention discloses a display panel and a crack detection method thereof and a display device. The display panel is provided with a display area and a non-display area. The display panel includes a dummy pixel circuit and a light emitting device connected to the dummy pixel circuit; the crack detection line is located in the non-display area, one end of the crack detection line is connected with the test terminal, the other end of the crack detection line is connected with the driving signal line, the driving signal line is connected with the dummy pixel circuit, and signals transmitted to the driving signal line by the crack detection line can control the dummy pixel circuit to drive the light emitting device to emit light. According to the technical scheme providedby the embodiment of the invention,the crack detection lines, the corresponding driving signal lines and the dummy pixel circuit are connected through the test terminals, and the test signal is transmitted to the light-emitting device connected with the dummy pixel circuit, thereby achieving the crack detection of the display panel, facilitating the implementation of a narrow-frame design, reducing the abnormality risk of a detection image, and improving the failure analysis efficiency of the display panel and the detection efficiency of a defective product.

The invention discloses a testing device and provides a testing device for a steering oil pump assembly, which has a simple structure, is convenient to use and can rapidly and accurately detect the steering oil pump assembly, and a testing method for the steering oil pump assembly. The invention solves the technical problems of high intensity, long detection period, high cost, incapability of carrying out durability test on each batch of new steering oil pump assembly and the like which are caused by the case that in the prior art, a steering oil pump can be detected only after being loaded. The testing device comprises a testing platform; the testing platform is provided with an oil pump fixing seat for fixing the steering oil pump assembly and a driving motor capable of driving the steering oil pump assembly to operate; an oil pipe is communicated between a high pressure oil outlet and a low pressure oil return port of the steering oil pump assembly; the oil pipe is provided with a pipeline control valve, a pressure valve and a flow valve.

The invention relates to the field of computers, in particular to a processor fault record generation method and apparatus. The processor fault record generation method comprises the steps of obtaining an instruction address in a current program counter (PC) of a processing unit through a JTAG channel when a control chip detects that the processing unit in a CPU stops responding, creating a first class table item comprising the instruction address in the current PC, and recording the first class table item in an instruction address table; and when the number of table items recorded in the instruction address table reaches a preset value, triggering CPU interrupt by the control chip. According to the scheme provided by the method and the apparatus, more information can be provided for processor fault analysis, so that the fault analysis efficiency is improved.

The invention discloses a power transmission and transformation system risk early warning method. The method includes the following steps that: S1, a power transmission line risk assessment establishing overall framework is established, a risk assessment model is established according to each component of a power transmission line, the quantization of state quantities is established, and the degrees of membership of the state quantities are solved; and S2, a calculation method and an evaluation standard for the correction of the risk value of the power transmission line by the operating years and operating environment of equipment and the operation status of a power grid are determined, and the aging coefficients of the components, the operating environment time coefficient and geographical position coefficient of the power transmission line are defined. With the power transmission and transformation system risk early warning method of the invention adopted, an interval of the power transmission line, where a fault occurs, can be determined more accurately, fault inspection can be performed in a targeted manner, the inspection range of line fault inspectors can be decreased, line fault inspection time can be decreased, the cause of the fault of the power transmission line can be determined more accurately, and the efficiency of fault analysis can be improved.

The invention discloses a gate oxide layer failure analysis method; a prepared TEM sample is bombarded by using an ionic beam having certain energy, Poly in the TEM sample is non-crystallized, the Poly lattice contrast cannot be showed in a transmission electron microscope, the contrast of heavy metals still remains, heavy metal polluted positions can be clearly observed under the transmission electron microscope, elemental analysis is successfully carried out, and thus the gate oxide layer failure analysis efficiency is effectively improved.

The invention relates to a converter fault diagnosis method based on kernel density estimation. The method comprises the steps of: performing pre-processing of collected data through cubic B-spline wavelet analysis based on a mallat algorithm to obtain samples with fault features; employing a KDE fault classifier to perform offline training to select better parameters of the fault classifier and accurately dividing the normal conditions and each type of fault condition included in the training samples, and using the better parameters into a classifier network to obtain the optimal parameters;implanting the classifier network with the optimal parameters into online simulation to perform real-time online monitoring fault diagnosis of an actual circuit; and allowing the classifier network with completion of optimal parameters to distinguish known fault type samples and normal samples, complete the location of the known fault types of faults and identify the unknown faults for achievementof circuit protection in a condition of generation of unknown types of faults. The converter fault diagnosis method based on kernel density estimation can determine the health condition of the converter more accurately and more reliably, and also can improve the efficiency of the fault diagnosis of the converter.

The invention discloses an auxiliary grid fault analysis system. The auxiliary grid fault analysis system comprises a main control module, wherein the main control module is connected with a plurality of paths of voltage input modules, a plurality of paths of current input modules, a plurality of switching value input modules, a high-capacity storage module, a human-computer interface, an external communication module and an auxiliary grid fault analysis system knowledge base; the three-phase voltage, the three-phase current waveform, the effective value, the period and the frequency are displayed in real time, and the single-phase or three-phase reactive power value, the active power value and the apparent power value are displayed in real time; one to eight alternating quantities are randomly selected from all alternating analog quantity channels, and the phasor diagrams are displayed; the first phasor phase fixedly serves as the reference, other phasors are based on the first phasor phase, drawing is carried out according to the phase corresponding to the reference phasor, and the effective value and the phase angle of the phasors are displayed; the positive sequence effective value, the positive sequence phase angle, the negative sequence effective value, the negative sequence phase angle, the zero sequence effective value and the zero sequence phase angle can be displayed in real time according to three-phase voltage or three-phase current, and the auxiliary grid fault analysis system has two harmonic analysis modes.

The invention discloses a crystal lattice dislocation detecting method. The method comprises the steps that an invalid device is selected for carrying out an electrical test, a voltage-current curve of the invalid device is scanned and measured repeatedly, and whether the voltage-current curve obtained through repeated scanning becomes larger or smaller is observed; the invalid device is roasted, the voltage-current curve of the invalid device is repeatedly measured again, and whether the voltage-current curve becomes larger or smaller is observed; if it is determined that the voltage-current curve of the device is changed, emission microscope positioning is carried out, and the dislocation range is reduced further; the device is ground, a focused ion beam is used for cutting the device, and a transmission electron microscope sample is formed through physical analytical sample preparation; a common transmission electron microscope observation way is adopted for dislocation observation to obtain a dislocation image. According to the crystal lattice dislocation detecting method, the dislocation is analyzed and the dislocation position is found from the electrical analysis process to the physical analysis process, the integrated circuit device invalidation analysis efficiency is improved, and the cost is reduced.

The invention provides an in-situ failure analysis sample table and a scanning electron microscope. The in-situ failure analysis sample table comprises a reversing portion, a clamping portion and a driving portion, wherein the reversing portion includes a first bevel gear and a second bevel gear, and the first bevel gear is meshed with the second bevel gear; the first bevel gear is sleeved and fixed on a first gear shaft; the second bevel gear is sleeved and fixed on a second gear shaft; the clamping portion is installed on the end part of the second gear shaft and used for clamping a sample;and the driving portion is connected with the first gear shaft and used for driving the first bevel gear to rotate, driving the second bevel gear to rotate in-situ and thus driving the sample to rotate by 360 degrees around the second gear shaft so as to achieve in-situ failure analysis of the sample.

The invention relates to an abnormal log processing method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps that when a terminal breaks down, if the terminal is in a preset special mode, storing an abnormal log of the terminal in a fixed partition of the terminal; and obtaining the abnormal log from the fixed partition, and returning the abnormal log to a server so as to analyze the abnormal log. The abnormal log can be uploaded in time, and rapid and accurate analysis can be carried out according to the abnormal log when the terminal cannot be started.