57 results about "Electrical analysis" patented technology

A recycling kiosk for recycling and financial remuneration for submission of a mobile telephone is disclosed herein. The recycling kiosk includes an inspection area with at least one camera and a plurality of electrical connectors in order to perform a visual analysis and an electrical analysis of the mobile telephone for determination of a value of the mobile telephone. The recycling kiosk also includes a processor, a display and a user interface.

A mini-kiosk for recycling and financial remuneration for submission of an electronic device such as a mobile phone is disclosed herein. The mini-kiosk is designed to be placed on a counter-top. The mini-kiosk includes electrical connectors and an inspection area with at least one camera in order to perform a visual analysis and an electrical analysis of the electronic device for determination of a value of the electronic device. The mini-kiosk also includes a processor and a display for user interaction.

A recycling kiosk for recycling and financial remuneration for submission of an electronic device such as a mobile phone is disclosed herein. The recycling kiosk includes electrical connectors and an inspection area with an upper chamber, a lower chamber, a transparent plate and at least one camera in order to perform a visual analysis and an electrical analysis of the electronic device for determination of a value of the electronic device. The recycling kiosk also includes a processor and a display for user interaction.

A method (400) of determining widths (W) and/or routes of I/O power routes (112) between one or more power distribution networks (108) and a plurality of I/O circuits (104) based on IR drop, electromigration, and electrostatic discharge electrical requirements. The method includes initially routing the I/O power routes and then iteratively analyzing the I/O power routes and iteratively incrementing the width of each power route that fails one or more of the electrical requirements until all power routes meet all electrical requirements. Once all power routes meet the electrical requirements, power routing is performed again to re-route any power routes as necessary to accommodate their wider widths. The method may be implemented in system (300) that includes a power routing tool (304), an electrical analysis tool (308), and a tool integrator (312) that implements an integrated power routing algorithm (316).

A method for optimizing a dechuck sequence, which includes removing a substrate from a lower electrode. The method includes performing an initial analysis to determine if a first set of electrical characteristic data of a plasma formed during the dechuck sequence traverses a threshold values. If so, turning off the inert gas. The method also includes raising the lifter pins slightly from the lower electrode to move the substrate in an upward direction. The method further includes performing a mechanical and electrical analysis, which includes comparing a first set of mechanical data, which includes an amount of force exerted by the lifter pins, against a threshold value. The mechanical and electrical analysis also includes comparing a second set of electrical characteristic data against a threshold value. If both traverse the respective threshold value, removes the substrate from the lower electrode since a substrate-released event has occurred.

The invention provides an analytical model for a saturable reactor for a converter valve. The saturable reactor for the converter valve consists of a coil and an iron core; and the working state of the iron core has a linear stage and a nonlinear stage under rated operation. In order to better perform electrical design and electrical analysis on the saturable reactor, the invention provides an analytical model for the saturable reactor for the converter valve. The analytical model comprises a coil resistance, a coil inductance, a core inductance, a core resistance, a terminal capacitance and other parameters. Corresponding electrical parameters of saturable reactors with different shapes and dimensions can be calculated. The analytical model has the advantages of clear physical conception, and capacities of easily acquiring each parameter needed in the model through a real object and providing a foundation for deep analysis of the saturable reactor.

The invention discloses a fabrication method for a protein electrochemical imprint sensor of a modified magnetic electrode by a one-step deposition method, and relates to the technical field of electrical analysis chemistry and protein recognition sensors. The fabrication method comprises the steps of 1) preparing a graphene@Fe3O4 nanometer composite material; 2) fabricating a graphene@Fe3O4@Au modified magnetic electrode by the one-step electrodeposition method; 3) introducing boric acid, amino and carboxyl active group into a surface of the modified magnetic electrode so that a plurality ofrecognition sites are provided for protein imprint; 4) pre-assembling protein; 5) performing electrochemical polymerization on a protein imprint membrane; and 6) washing template protein with an eluent so as to build the protein molecular imprint electrochemical sensor. The magnetic modified electrode fabricated by the method is beneficial for introducing the active group, increasing the recognition sites, improving selectivity, expanding surface area and improving conductivity of electrode surface, the built protein imprint electrochemical sensor is high in sensitivity and can be used repeatedly, and target protein can be specially recognized.

The present disclosure relates to a system and method for determining an effective electrical resistance in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design and identifying one or more features associated with the electronic circuit design. Embodiments may also include performing a resistance only extraction of a circuit net associated with the electronic circuit design and identifying at least two node locations from the electronic circuit as one or more port nodes. Embodiments may further include reducing the resistance only extraction to an equivalent circuit including only the port nodes and attaching a high-resistance ground voltage source to at least one of the port nodes of the reduced equivalent circuit. Embodiments may also include generating a conductance matrix, based upon, at least in part, the reduced equivalent circuit.

The invention discloses a measurement method of word line resistance of a 3D NAND, and belongs to the technical field of a semiconductor. The measurement method comprises the steps of providing a 3D NAND sample (there is no via in an array region); performing grinding on a metal layer of the 3D NAND sample until channel hole plugs appear; performing grinding on a first stage region of the 3D NANDsample until all word lines in the first stage region are exposed, and performing metal depositing to enable all exposed word lines to be connected; performing measurement on the sum of resistance oftwo adjacent word lines in a second stage region of the 3D NAND sample, and on the sum of resistance of the first word line and the last word line; and calculating the resistance of each word line according to the measured sum of resistance. By virtue of the measurement method, measurement of resistance of all word lines in the 3D NAND sample is realized quickly and accurately, thereby providing basis for electrical analysis of the 3D NAND and promoting smooth research and development of the 3D NAND product.

The invention discloses a method for detecting a failure mechanism of automatic dialing of a mobile phone, which comprises the following steps specified in the standard: baking, physical isolation of failure point locating, electrical analysis of failure point locating, and microsection analysis. The method can be used for quickly locating the failure point, so as to determine the party responsible for the failure and generate technical innovation references, thereby avoiding reoccurrence of similar failures.

The invention relates to the field of power electronics and power systems, in particular to a method for modeling an electrical analysis model of a saturable reactor for a converter valve. In the invention, on the basis of analyzing the electrical properties of a converter valve assembly and a saturable reactor, serial and parallel forms of all electrical assemblies of an equivalent circuit of the saturable reactor are provided; and on the basis of the topological relation of the equivalent circuit, nonlinear relations of two parameters of an iron core inductor and an iron core loss equivalent resistor with current flowing through an iron core inductor branch are expressed in the form of a mathematical formula. Proved by tests, the saturable reactor manufactured with the technological level at present meets the mathematical formula, thereby the scientificity of the formula is further verified.

The invention relates to a method for detecting inner circuits in PCBs (printed circuit boards) by software GENESIS. The method includes opening a backup drawing in the software GENESIS, closing attributes of other circuit layers of the drawing, and reversing attributes of an inner backup layer and a pore layer; subtracting a line width value of an inner circuit of a positive plate by a minimum line width required and allowed by process, adding minimum interval required and allowed by the process to spacing of the inner circuit of a negative plate, and performing electrical analysis of the inner layer; and locating independent thin lines unsatisfactory to the process according to open circuit contacts in reports of the inner layer electrical analysis. Existence of the thin lines unsatisfactory to the process in the inner circuits of the circuit boards can be judged accurately and quickly by the method, correction is made timely before production, defectiveness and scrappage of formed products are avoided, and cost is saved for manufactures effectively.

The invention discloses a short-circuit current analysis system, comprising: a GIS interface, a database, a short-circuit analysis module, and several clients. The short-circuit analysis module includes a processor, a topology and an electrical analysis module. The client is connected to the short-circuit analysis module, which is connected to the Database, database connection GIS interface. The invention also discloses an analysis method of the short-circuit current analysis system. It can realize the timely detection and evaluation of the short-circuit fault in the circuit, guarantee the safety of the circuit operation, and provide a reliable evaluation method for the troubleshooting of the circuit fault. It is of great significance to the normal operation of the circuit.

Embodiments of the present disclosure relate to a compact opto-electric probe. Described are various configurations for performing efficient optical and electrical testing of an opto-electrical device using a compact opto-electrical probe. The compact opto-electrical probe can include electrical contacts arranged for a given electrical contact layout of the opto-electrical device, and optical interface with a window in a probe core that transmits light from the opto-electrical device. An adjustable optical coupler of the probe can be mechanically positioned to receive light from the device's emitter to perform simultaneous optical and electrical analysis of the device.

A system utilizes a laser to remove the mold compound of an IC without damaging the internal die, wire leads, solder connections and any other critical structures encapsulated within the mold compound, thereby leaving them available for the provisional and electrical analysis. A laser beam is focused through appropriate optics onto a plane corresponding to the surface of an IC. A layer of material which is opaque at the wave length of the laser beam is applied at the surface of the IC chip to be ablated prior to each pass of the laser. A spray nozzle may be provided to move in synchronous motion ahead of the laser being to apply coat of the opaque material.

The invention discloses an intelligent electrical control system for a building. A building collection unit is used for collecting the data information of the building, and an electrical collection unit is used for collecting the electrical information of the building. A data positioning module is used for positioning and processing coordinates of floors and building households on the building, and coordinate processing information is obtained; a data analysis module is used for receiving the data information and the electrical information, analyzing the data information to obtain data analysis information, analyzing the electrical information to obtain electrical analysis information, and combining the data analysis information and the electrical analysis information to obtain a data analysis set; a data processing module is used for receiving the data analysis set and processing the data analysis set to obtain a data processing set, and an early warning control module is used for early warning, regulating and controlling the electrical state of the building according to the data processing set; the system is used for solving the problem that the electrical operation state of each building user in a building cannot be monitored, and the problem that early warning and regulation are carried out on the building user in an abnormal state.