AXI protocol-based high-performance DDR controller and data transmission method

Abstract

The invention discloses an AXI protocol-based high-performance DDR controller and a data transmission method. The data input end of the controller is connected with an AXI bus, and the data output end of the controller is connected with a DDR memory. The controller structurally comprises an AXI interface module, a register configuration module, a data caching module, a control module, a time sequence module and a data transmission module. Compared with the prior art, the AXI protocol-based high-performance DDR controller and the data transmission method have the advantages that efficient memory access work is finished; the performance of the overall system is improved; the project demands can be better met; the project budget can be reduced; the internal logic and structure of the DDR controller are well improved through the method; the data transmission efficiency is effectively improved; the practicality is high; and the implementation and popularization are facilitated.

Description

technical field [0001] The invention relates to the field of computer application technology, in particular to a high-performance DDR controller based on the AXI protocol and a data transmission method with strong practicability. Background technique [0002] With the advancement of circuit design and production technology, the processing capacity of CPU continues to increase at a high speed, and the difference between the operating frequency of the processor and DRAM will greatly reduce the performance of the entire system. Improving the bandwidth of the bus and the work efficiency of each device has become a key to improving the system. key to performance. Due to the high performance of the AXI bus itself and the wide application of ARM microprocessors, AXI has become a widely used bus standard in SOC design. In SOC design, due to the use of less-capacity cache and a simpler storage system than ordinary computer architectures, memory access performance has a greater impac...

AI Technical Summary

Problems solved by technology

In SOC design, due to the use of less-capacity cache and a simpler storage system than ordinary computer architectures, memory access performance has a greater impact on the entire system. When the physical parameters of the memory are determined, the design of the storage interface will be Directly affect the performance of the storage part, thereby affecting the performance of the entire system

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