Voltage resisting power MOS device
A MOS device and power technology, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of low breakdown voltage and reduced process complexity, and achieve the goal of improving drain-source withstand voltage, easy implementation, and improved withstand voltage performance Effect
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Embodiment 1
[0016] see figure 1 . This embodiment is based on a CMOS process and uses a VDMOS device in which N is implanted into a drift region. It includes a drift region 1, a gate 2, a source 3, a source injection region 4, a channel injection region 5, a low dielectric constant dielectric column region 6, an N+ injection region 7, a gate insulating layer 8, and a drain 9. Among them, the low dielectric constant dielectric residential region 6 is in direct contact with the drift region 1, and is located on both sides of the drain-source current path, so that the electric field potential energy line in the drain-source path is affected by the low dielectric constant region, and the potential energy line is in the low-dielectric constant region. The vicinity of the dielectric constant region is pulled, and the result is that the originally concentrated electric field potential energy lines in the drain-source path become more sparse, which directly improves the breakdown voltage, and th...
Embodiment 2
[0019] see image 3 . This embodiment is based on a CMOS process, including an n drift region 1, a gate 2, a source level 3, a source implantation region 4, a p drift region 5, a low dielectric constant dielectric region 6, an N+ implantation region 7, and a gate insulating layer 8, drain 9. This embodiment is a VDMOS device with a non-trench structure, wherein the low dielectric constant dielectric region 6 is in direct contact with it in the drift region 1, and the VDMOS drain-source current path is located on both sides of the low dielectric constant dielectric region 6, so that the drain-source The electric field potential energy lines between are pulled when they pass through the vicinity of the low dielectric constant dielectric region 6, so that the originally more densely concentrated electric field potential energy lines become slightly sparser, so that the breakdown voltage of the VDMOS device is improved. In this example, no high-K dielectric material is used for ...
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