Clock circuit and clock signal transmission method thereof

Abstract

The invention provides a clock circuit and a clock signal transmission method thereof. The clock circuit comprises a buffer module, N multiplexers and N clock gating cells, wherein the buffer module comprises an input end and N output ends, and is used for enhancing the driving capabilities of clock signals received at the input end and outputting clock signals of which the driving capabilities are enhanced from the N output ends; the N output ends are connected with data ends of the N clock gating cells one by one; output ends of the N multiplexers are connected with enabling ends of the N clock gating cells one by one; and the clock gating cells are used for outputting the clock signals from the output ends according to frequency division logic signals or gating logic signals received by the enabling ends from the output ends of corresponding multiplexers and the clock signals received by the data ends from the output ends of the buffer module. Through the technical scheme of the invention, a clock path can be shortened; the transmission delay of a clock source signal is reduced; and the power consumption of the clock circuit is lowered.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a clock circuit and a method for transmitting a clock signal. Background technique [0002] In a digital integrated circuit, the data transmission between each unit is controlled synchronously by a clock signal. When a clock circuit with a traditional structure is used in a digital integrated circuit, too many logic units on the clock path in the clock circuit will make the propagation path of the clock signal too long, resulting in a comparison of clock delay and power consumption on each clock path Big. Contents of the invention [0003] Embodiments of the present invention provide a clock circuit and a method for transmitting a clock signal using the clock circuit, which can reduce clock delay and reduce power consumption of the clock circuit. [0004] In a first aspect, a clock circuit is provided, including a buffer module, N first multiplexers, and N clock gating units, where N ...

AI Technical Summary

Problems solved by technology

When a clock circuit with a traditional structure is used in a digital integrated circuit, too many logic units on the clock path in the clock circuit will make the propagation path of the clock signal too long, resulting in a comparison of clock delay and power consumption on each clock path Big

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