A Wiring Method of Adder Supporting Pin Swapping

Abstract

An adder wiring method supporting pin swapping. The method comprises: locking a full adder, and determining that at least one input end in the full adder needs to receive an input signal (m) from the outside of a PLB; determining whether a first look-up table (LUT1) has an unused input end (F4); where the unused input end exists, switching the input signal (m) from the outside of the PLB to the unused input end (F4) of the first look-up table (LUT1); and connecting an output end (x) of the look-up table to at least one input end (a) of the full adder. According to the wiring method, a pin swapping technique is extended to a full adder based on a chip architecture of C1. By using the full adder, logical resources are saved, and the utilization rate of a chip is effectively improved. At the same time, with the aid of interchangeability of two input port pins of the full adder and unused input and output ports of a front end LUT, connectivity and fmax of the full adder are improved by means of the pin swapping technique, and the full adder can select a pathway for wiring, thereby expanding a solution space for wiring, and reducing the overall power consumption of the chip.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an adder wiring method supporting pin exchange. Background technique [0002] Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) is a logic device with abundant hardware resources, powerful parallel processing capability and flexible reconfigurable capability. These features make FPGA more and more widely used in data processing, communication, network and many other fields. [0003] As a basic operation, addition is widely used in various algorithms of digital signal processing and digital communication. Because the adder is used frequently, its speed often affects the operating rate of the entire system. Inside an FPGA, an adder is usually implemented by a carry chain. figure 1 It is a schematic diagram of the logical structure of the full adder in the prior art, such as figure 1 As shown, the full adder includes a look-up table LUT (Look-Up Tab...

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Problems solved by technology

[0004] In the FPGA chip, due to the limitations of the FPGA chip and the hardware architecture of the full adder, usually only a relatively small number of winding paths can be connected from the XBAR, which limits the number of input signals and increases the complexity of wiring. degree, reducing the success rate of wiring

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