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Formation method of semiconductor structure

A semiconductor and dummy gate technology, applied in the field of semiconductor structure formation, can solve the problem that the performance of input and output devices cannot meet the needs of technological development, and achieve the effect of avoiding excessive size and improving performance

Active Publication Date: 2019-09-27
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the performance of input and output devices in semiconductor devices formed by the prior art still cannot meet the needs of technological development

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Experimental program
Comparison scheme
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Embodiment Construction

[0030] It can be seen from the background art that the semiconductor structure formed in the prior art has the problem of poor performance of input and output devices. Now combine the formation of input and output devices in the prior art to analyze the reasons for its poor performance:

[0031] Since the operating voltages of the core device and the input and output devices are different, the thicknesses of the gate dielectric layers of the core device and the input and output devices are different. Specifically, the thickness of the gate dielectric layer of the input-output MOS device is usually greater than the thickness of the gate dielectric layer of the core MOS device.

[0032] In the conventional method for forming a semiconductor structure, an oxide layer and a dummy gate are usually formed first, and after forming a source region and a drain region, the dummy gate is removed to form an opening, and a metal gate is formed in the opening. The process of forming the me...

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Abstract

Disclosed is a formation method of a semiconductor structure. The formation method comprises the steps of forming a base, wherein the base comprises a peripheral region used for forming input and output devices and a core region used for forming a core device; forming pseudo gate structures on the base; forming a dielectric layer on the base between the pseudo gate structures; removing pseudo gates of the pseudo gate structures in the peripheral region to form a first opening; performing oxidization treatment on an oxide layer exposed at the bottom of the first opening; removing pseudo gates of the pseudo gate structures in the core region and the oxide layer to form a second opening; forming a gate dielectric layer; and filling the first opening and the second opening with a metal layer. The oxidization treatment adopted in the formation method is only performed on the oxide layer exposed at the bottom of the first opening, so that the oxidization treatment does not influence the side walls of the pseudo gate structures in the core region; and therefore, overlarge dimension of the metal layer for filling the first opening and the second opening can be avoided, thereby improving the performance of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. Transistor (MOS), as the most basic semiconductor device, is currently being widely used. [0003] Semiconductor devices are mainly divided into core (Core) devices and input and output (Input and Output, IO) devices according to their functions. Wherein, the core device includes a core MOS device, and the input-output device includes an input-output MOS device. In order to reduce the size of the semiconductor device and improve the integration of the semiconductor device, the size of the core device is smaller than the size of the input and output devices. In addition, the operating voltage of the input and output devices is muc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP