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A semiconductor wafer level packaging method

A wafer-level packaging and semiconductor technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, and electrical solid-state devices, etc., can solve the problems of easy cutting blade deviation, large scribing slot occupation area, and no resin material on the side of the chip. Achieve the effect of easy alignment and improved yield

Active Publication Date: 2021-02-19
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In the existing wafer-level packaging method, the secondary dicing method is generally adopted. Firstly, the dicing groove is formed by pre-cutting, and then the wafer is cut into individual chips by secondary dicing. Usually, the dicing groove formed by pre-cutting has a relatively large width. , the blade is easy to cut off during the second cutting, so that the side of some chips is not protected by resin material, and the wider dicing groove occupies a larger area, making the utilization rate of the wafer not high

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  • A semiconductor wafer level packaging method
  • A semiconductor wafer level packaging method
  • A semiconductor wafer level packaging method

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Embodiment Construction

[0015] see figure 1 , figure 1 It is a schematic flow chart of an embodiment of the semiconductor wafer-level packaging method of the present invention, and the method includes the following steps:

[0016] S101: Provide a semiconductor wafer, the wafer is equipped with a number of chips arranged in a matrix, and there are dicing grooves between the chips; the wafer includes the front and the back, the front of the chip is the front of the wafer, and the back of the chip is the back of the wafer ;

[0017] Specifically, combine figure 2 , figure 2 It is a structural schematic diagram of an embodiment of a semiconductor wafer. The wafer 100 has a front side and a back side, wherein the front side is a functional side and the back side is a non-functional side. The front side of the wafer 100 is arrayed with a plurality of chips 10 , and a plurality of dicing slots 20 are arranged between the chips 10 . Wherein, the chip 10 is one of a silicon substrate, a germanium subst...

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Abstract

The invention discloses a semiconductor wafer-level packaging method. The packaging method includes: providing a semiconductor wafer, the wafer is provided with a plurality of chips arranged in a matrix, and dicing grooves are provided between the chips; The chip includes a front and a back, the front of the chip is the front of the wafer, the back of the chip is the back of the wafer; Grooves; dicing is aligned to the area between the two grooves, so as to separate at least two of the chips. Through the above method, the present invention pre-cuts to form a groove with a small width, and the blade is easy to align during the secondary cutting, thereby increasing the yield and improving the utilization rate of the wafer.

Description

technical field [0001] The invention relates to the field of semiconductor chips, in particular to a semiconductor wafer-level packaging method. Background technique [0002] The mounting shell for the semiconductor integrated circuit chip plays the role of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance. It is also a bridge to communicate the internal world of the chip and the external circuit. These pins are connected to other devices through wires on the printed board. Therefore, the packaging of semiconductor devices plays an important role for central processing units and other large-scale integrated circuits. [0003] In the chip packaging structure, wafer level packaging is to package and test on the whole wafer, then plastic seal it, and then cut it into individual chips. [0004] In the existing wafer-level packaging method, the secondary dicing method is generally adopted. Firstly, the dicing groove is formed by pre-cutt...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/78H01L21/304
CPCH01L21/3043H01L21/78H01L24/94
Inventor 高国华朱桂林
Owner NANTONG FUJITSU MICROELECTRONICS