A Multi-input High Speed ​​CMOS Buffer Circuit

Abstract

The invention discloses a multi-input high-speed CMOS buffer circuit. The buffer circuit comprises a voltage-to-current module, a multipath selector module, and a current-to-voltage module, wherein two sides of the multipath selector module are respectively connected with the voltage-to-current module and the current-to-voltage module, the other side of the voltage-to-current module is used for inputting the voltage, and the other side of the current-to-voltage module is used for outputting the voltage; the voltage-to-current module is used for converting multiple input voltage into a current signal; the multipath selector module is used for conducting the voltage-to-current module and the current-to-voltage module; the current-to-voltage module is used for converting the input current signal into a voltage signal and outputting the voltage signal. The multi-input high-speed CMOS buffer circuit disclosed by the invention has the excellent characteristics of being fast in buffering speed, small in delay, free from using a bootstrapping switch, and strong in usability.

Description

technical field [0001] The invention relates to a buffer circuit, in particular to a multi-input high-speed CMOS buffer circuit. Background technique [0002] In modern CMOS analog circuits, the buffer circuit is a very commonly used circuit. The buffer has the characteristics of high input impedance, low output impedance, and high driving capability, and is widely used in various ADCs, DACs, and various SOC chips. At present, the industry has higher and higher requirements for buffers in terms of high speed, low power consumption, and low noise. [0003] In a traditional buffer application environment with multiple input signals, the input voltages of multiple input signals are generally selected and connected to the buffer through multiple switches, and then directly output in the form of voltage. This kind of buffer circuit has the following defects: (1) due to the certain impedance and capacitive reactance of the switches, the more switches will cause a larger time del...

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Problems solved by technology

This kind of buffer circuit has the following defects: (1) due to the certain impedance and capacitive reactance of the switches, the more switches will cause a larger time delay, which will slow down the processing speed of the buffer; speed, it is usually necessary to increase the bias current of each branch of the circuit, which will lead to a large power consumption of the circuit, (3) when the input signal is too large, a bootstrap switch is required, which increases the complexity of the use of the buffer

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