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Memory system, memory module and control method thereof

A memory module and memory controller technology, applied in the field of memory, can solve problems such as inability to optimize signal quality, and achieve accurate impedance matching

Active Publication Date: 2017-08-29
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional on-chip terminations are usually connected to a reference voltage such as ground, however, this design does not optimize signal quality

Method used

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  • Memory system, memory module and control method thereof
  • Memory system, memory module and control method thereof
  • Memory system, memory module and control method thereof

Examples

Experimental program
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Embodiment Construction

[0015] Please refer to figure 1 , figure 1 is a diagram illustrating a storage system 100 according to an embodiment of the invention. Such as figure 1 As shown, the storage system 100 includes a memory controller 110 and a memory module 120 powered by a power supply voltage VDD. The memory module 120 includes a memory interface circuit 122 , a control circuit 124 and a memory array (memory array) 126 . In this embodiment, the memory controller 110 and the memory module 120 are connected through a plurality of connection lines, and the connection lines are used to transmit a plurality of bidirectional data signals DQ, a write clock signal WCK, an inverted write clock signal (inverted write clock signal) clocksignal) WCKB, a plurality of command signals CMD, a clock signal CLK, and an inverted clock signal CKB. In other embodiments, the write clock signal WCK and the clock signal CLK can be collectively referred to as clock signals, for example, they can be referred to as th...

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Abstract

The invention provides a memory system, a memory module and a control method thereof. The memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module is coupled to the memory controller, receives the at least a clock signal and the inverted clock signal from the memory controller, and includes a first terminal resistor, a second terminal resistor and a switch module, wherein a first node of the first terminal resistor is to receive the clock signal, a first node of the second terminal resistor is to receive the inverted clock signal, and the switch module is coupled between the first terminal resistor and the second terminal resistor and is arranged for selectively connecting or disconnecting a second node of the second terminal resistor to a second node of the first terminal resistor. Briefly summarized, the clock signal is allowed to connect the inverted clock signal in die. Therefore, the impedance matching can be more accurate, and the reflection of the signal can be lowered to improve the signal integrity.

Description

technical field [0001] The invention relates to the field of memory, in particular to a memory system with an improved on-die termination (ODT) structure, a memory module and a control method for the memory module. Background technique [0002] A traditional dynamic random access memory (DRAM) module usually includes an on-die termination (ODT) for impedance matching of a signal line, and signal distortion can be reduced by using the on-die termination. Traditional on-chip terminations are usually connected to a reference voltage such as ground, however, this design does not optimize signal quality. Contents of the invention [0003] In view of this, the present invention provides a storage system, a memory module and a control method thereof to solve the above problems. [0004] According to at least one embodiment, there is provided a memory system comprising: a memory controller for selectively generating at least a clock signal and an inverted clock signal; and a memo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4096
CPCG11C11/4096G06F13/4086G11C5/04G11C7/1087G11C7/1093G11C7/222G11C7/225H03K19/0005H04L25/0298G11C2207/105G11C11/4076G11C11/4093G06F13/1668G11C5/06G11C7/22
Inventor 陈尚斌谢博伟
Owner MEDIATEK INC
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